Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: FreedomChip
Edited by the Electronicstalk Editorial Team on 23 January 2007
Switch to ASIC
cuts FPGA production costs
Lattice Semiconductor has announced the FreedomChip cost reduction methodology for its Extreme Performance LatticeSC and LatticeSCM FPGA families
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Customers can reduce the price of selected high volume LatticeSC/M FPGA designs from 30 to 75% by converting to the pin compatible Lattice FreedomChip device with a fully integrated, seamless design methodology. The FreedomChip methodology is a completely new approach to the challenge of FPGA cost reduction that employs industry standard ASIC techniques to comprehensively test a LatticeSC/M die to the customer's specific design.
Through automatic insertion of scan logic and dedicated silicon test features, the customer's netlist is implemented in low-cost, custom-tested silicon.
This eliminates the difficult and error prone back-end design conversion associated with traditional structured ASICs.
The FreedomChip approach is the first FPGA-based design methodology to employ comprehensive scan-based test structures in the fabric specifically to achieve these results.
Fault coverage of over 99% typically is achieved using these test techniques for any given design and device.
'The use of proven ASIC test techniques in an FPGA fabric sets FreedomChip distinctly apart from other approaches to FPGA cost reduction', said Doug Foster, Lattice Director of Test Development and FreedomChip Programme Manager.
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'By utilising the standard FPGA die as a platform, the FreedomChip methodology is able to provide customers with significantly lower NREs and faster time to market than is possible with ASICs or structured ASICs while maintaining complete timing compatibility'.
Timing errors are the number one cause of ASIC and structured ASIC respins, and this trend is expected to worsen on future technologies.
Using the new design methodology, Lattice customers will be able to design, debug and move into production their end-system products using standard LatticeSC/M FPGAs while minimising design effort and maximising flexibility as the system design matures.
Once high volume manufacturing is needed, FreedomChip equivalents can be ordered from Lattice with a minimum quantity ranging from as low as 1200 to 3600 pieces (depending on device density) delivered in 12 weeks or less.
Although the FreedomChip methodology custom-tests the FPGA core and interconnect for the specific design, all I/O and block-level functions (MACO blocks, serdes, memory etc) remain user-configurable and programmable, allowing additional flexibility to tune design parameters without redesign.
The new FreedomChip cost reduction solution initially will support all LatticeSC and LatticeSCM devices manufactured in flip chip packages.
These devices range from the 25,000-LUT LatticeSC/M25 in the 1020-ball flip-chip BGA (fcBGA) to the 115,000-LUT LatticeSC/M115 in the 1704-ball fcBGA package.
All speed grades of each device are supported by the FreedomChip methodology.
The FreedomChip methodology is integrated into Lattice's ispLever software design tool suite - no additional software is required.
When using ispLever's FreedomChip mode, necessary logic is added automatically to allow full scan testing, seamlessly and transparently.
Using this methodology, the design can be targeted toward both a LatticeSC/M FPGA and a FreedomChip device simultaneously.
This means that a design that targets the FreedomChip flow from the outset can be used first on standard LatticeSC/M FPGAs for initial production builds and then replaced with the reduced cost FreedomChip devices for actual production with no additional design work or time required.
The FreedomChip cost reduction methodology is embedded into Lattice's ispLever design tool suite: there is no added cost for the FreedomChip design capability.
Lattice's ispLever Version 6.1 Service Pack 2 is being provided to Lattice customers to support initial designs.
NRE charges for FreedomChip are US $75,000 for a single design on any device supported.
In high volume (25,000-plus pieces), cost reductions compared with the standard LatticeSC/M devices range from 30% per unit for the LatticeSC/M25 to 75% for the LatticeSC/M115.
Production volumes of FreedomChip versions of the LatticeSC/M family are scheduled for Q2 2007.
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