Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: IspClock5300S family
Edited by the Electronicstalk Editorial Team on 01 November 2006
Programmable clock buffers have more
outputs
In-system-programmable zero-delay single-ended clock buffer family expands with 16- and 20-output devices.
Lattice Semiconductor has expanded its ispClock5300S family of in-system programmable, zero-delay, single-ended clock buffer devices with the production release of the pin-compatible ispClock5316S (16-output) and the ispClock5320S (20-output) ICs The E2CMOS-based ispClock5300S device family now offers programmable clock skew, termination and interface standard support in a series of five devices with four to 20 outputs
This article was originally published on Electronicstalk on 21 Jun 2006 at 8.00am (UK)
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"Our ispClock5300S family provides ideal low-cost clock distribution devices for any microprocessor-based system", said Stan Kopec, Lattice Corporate Vice President of Marketing.
"Using a single chip to fan out all clocks from a single source avoids timing issues due to cascading".
"With these new devices, the ispClock5300S family now can address all clock distribution applications which require zero delay buffers and fan-out buffers with up to 20 outputs".