Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: IspClock5300S family
Edited by the Electronicstalk Editorial Team on 21 June 2006
Programmable clocks suit smaller systems
Family of in-system-programmable zero-delay single-ended clock buffer devices adds cost-effective eight- and four-output options.
Lattice Semiconductor has expanded its ispClock5300S family of in-system programmable, zero-delay, single-ended clock buffer devices, with the production release of the new ispClock5308S (eight-output) and the ispClock5304S (four-output) chips These new devices provide lower cost alternatives to the previously announced 12-output ispClock5312S
This article was originally published on Electronicstalk on 1 Nov 2006 at 8.00am (UK)
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All three members of the E2CMOS-based ispClock5300S device family are pin compatible and offer programmable clock skew, termination and interface standard support.
The ispClock5300S devices support four operating configurations, including zero-delay buffer mode, combined zero-delay and non-zero-delay fan-out mode, dual fan-out buffer mode and fan-out buffer mode with output dividers.
"Our ispClock5300S device family is an ideal low cost clock distribution device for any microprocessor-based system", said Stan Kopec, Lattice Corporate Vice President of Marketing