Intersil I2C buffers minimise idle bus time

Intersil has announced a series of two-wire bidirectional I2C buffers that enable error-free data transmission in heavily-loaded I2C bus configurations.

The ISL3300x series, which includes the ISL33001, ISL33002 and ISL33003, is said to be ideal for use in servers, networking and telecommunications infrastructure equipment, and other applications that need hot-swap board insertion and bus isolation.

The buffer minimises bus idle time and propagation delay, increasing maximum overall system speed.

Hot-swap capability prevents corruption of data and clock lines when I2C devices are plugged into live backplanes, so users can exchange boards on a live bus with no data disruption.

All three versions are capable of 400kHz operation (I2C fast-mode delivery rate) and operate on 2.3-5.5V supplies.

All of the ISL3300x buffers also include rise-time accelerator circuitry to improve signal integrity and reduce power consumption from passive bus pull-up resistors.

Each device also includes features designers can apply in specific applications.

For example, the ISL33002 and ISL33003 incorporate a logic level translator, so devices can be interfaced at mixed logic voltage levels.

The ISL33001 and ISL33003 include an enable pin for low-current shutdown, while the ISl33002 provides an accelerator disable pin.

The ISL3300x series is available in compact, space-saving, eight-lead 3x3 TDFN and eight-lead MSOP packages.

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