Product category: Standard Logic Devices
News Release from: IDT | Subject: TeraClock family
Edited by the Electronicstalk Editorial Team on 6 January 2003
Zero delay buffers
and programmable skew devices
IDT has strengthened its clock management portfolio with the introduction of its TeraClock family of zero delay buffers and programmable skew devices
The devices provide the industry's broadest range of translation capabilities between I/O standards with five user-configurable single-ended or differential signal variants at the input and four signal variants at the output, as well as uniquely offering pin-to-pin compatibility for ease of migration between the zero delay buffer and programmable skew devices.
This article was originally published on Electronicstalk on 6 January 2003 at 8.00am (UK)
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The new IDT TeraClock devices operate at frequencies up to 250MHz, making them ideal in high-speed applications, while offering 50ps cycle-to-cycle jitter and 100ps output to output skew.
IDT TeraClock devices support the high-speed I/O standards required in next-generation communications applications, such as network routers, wireless 3G basestations and storage area networks.
Overall system integrity and reliability is ensured through redundant clock and hitless switchover features.
The IDT TeraClock products support single-ended 2.5V TTL, 1.8V LVTTL; differential 2.5V LVTTL, 1.8V LVTTL, HSTL, eHSTL and LVPECL; and pseudodifferential 2.5V TTL, 1.8V TTL, HSTL, eHSTL and LVPECL input signals, and HSTL, eHSTL or 1.8V/2.5V LVTTL outputs in various combinations.
In addition to the noted input signals, the IDT programmable skew TeraClock devices also include programmable skew output signals.
Additionally, the IDT TeraClock family uniquely offers zero delay buffers and programmable skew devices that are pin-to-pin compatible, allowing designers the flexibility to easily migrate between the two devices to optimise for cost and performance.
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