Product category: Design and Development Software
News Release from: IBM Haifa Research Lab
Edited by the Electronicstalk Editorial Team on 11 March 2005
Collaborative research begins
to bear fruits
A collaborative effort between European companies, universities and the European Union has produced advanced technologies which could improve chip making productivity by up to 30%
IBM revealed this week at the DATE technical conference that a collaborative effort among several European companies, universities and the European Union to change the way microchips are designed has produced advanced technologies which could improve chip making productivity by up to 30%. The EU last year awarded Eur 7 million to a consortium of three companies and four universities with the purpose of encouraging the development and deployment of new tools and methodologies that will increase chip design productivity and reduce time to market.
Related stories
Project promotes self-healing software
IBM Haifa researchers recently hosted the first meeting to launch Shadows, the European Commission's Eur 5 million research project to promote the design of self-healing software systems
Machine learning and simulation-based verification
Now in its third-year at the IBM Haifa Research Lab, the Coverage-Directed Generation project, known as CDG, is being successfully used for simulation-base verification
The collaborative research effort - known as Prosyd - is centred around a specification language known as PSL and PSL-based tools and methodologies.
PSL, based on the Sugar language from IBM, is a powerful, concise language for assertion specification and complex modelling.
As an emerging standard, PSL provides an interoperation language that enables engineers to exchange hardware specifications and develop seamless tool integration.
The key result of the joint investment so far is in an impressive collection of tools developed by the members of the consortium which interoperate around the emerging PSL standard.
In particular, the IBM tools provide powerful PSL-based solutions for the vital process of chip verification; that is, the demanding need to ensure that every one of the millions and millions of individual chip circuits actually work according to spec.
Further reading
Property Specification Language recognised
The Accellera Property Specification Language (PSL) version 1.1 has been recognised by a DesignVision award from the International Engineering Consortium (IEC)
Lightweight formal verification platform
IBM is offering RuleBase Single-Thread Edition (SE), a lightweight version of its RuleBase formal verification platform as an entry-level product for those looking for a small scale solution
Modelling technology goes open source
Ameos is now available under terms based on the Gnu Lesser General Public Licence as OpenAmeos
'The new IBM tools incorporate the use of the PSL standard, which together with advanced algorithms is opening up new directions in formal verification of larger designs', said Moshe Molcho, who manages IBM's Haifa Development Lab.
'Engineers can now reduce development costs, design higher quality electronic systems, and offer them to customers faster than in the past by including these tools into the way they do business'.
IBM will offer the tools in Europe through IBM Engineering and Technology Services, a well-established 'engineering on demand' business unit with such well-known clients as Boeing, Honeywell, Sony, Microsoft and many others.
Some of the industry-first PSL-based tools and methodologies being offered by IBM E and TS in Europe include the IBM DV RuleBase PE and IBM DV FoCs assertion compiler, developed at the IBM Haifa Research Lab as part of the Prosyd project.
RuleBase PE is a formal verification solution which exhaustively checks all possible behaviours of the chip while still on the designer's desk, and offers a mathematical guarantee for their validity while leveraging parallel computing techniques.
The FoCs assertion compiler translates PSL assertions into HDL checkers, which are integrated into the simulation environment.
These checkers monitor chip simulation results on a cycle-by-cycle basis for violation of assertions.
'We foresee ample innovations in chip design and verification made possible using the property-based design and verification techniques enabled by Prosyd', says Dieter Muenk, General Manager of E and TS for IBM in Europe.
'This new offering demonstrates IBM's continued commitment to serving our customers by rapidly bringing state-of-the-art design and verification technologies to the marketplace'.
• IBM Haifa Research Lab: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
Eds Sales Take A Tumble
Dave Friedlos, Computing , Thursday 17 May 2007 at 00:00:00 But experts say downturn may reflect market weakness, writes Dave Friedlos Outsourcing giant EDS has released disappointing first-quarter figures showing slower growth and fewer con
Sweet specialist sees growth spurt
Lara Williams, Computing , Thursday 17 May 2007 at 00:00:00 Confectionary company IT infrastructure overhaul accommodates rapid growth Confectionery supplier Bon Bon Buddies has overhauled its IT infrastructure to cope with rapid growth whic
Canon takes a better picture of its supply chain
Lara Williams , Computing , Thursday 17 May 2007 at 00:00:00 Imaging specialist improves sales forcasting by 20 per cent Imaging specialist Canon has improved the accuracy of product sales forecasting by more than 20 per cent using supply ch
Search the Pro-Talk network of sites
