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News Release from: IBM Haifa Research Lab
Edited by the Electronicstalk Editorial Team on 8 November 2004

Lightweight formal verification platform

IBM is offering RuleBase Single-Thread Edition (SE), a lightweight version of its RuleBase formal verification platform as an entry-level product for those looking for a small scale solution.

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IBM today announced that it is offering RuleBase Single-Thread Edition (SE), a lightweight version of its RuleBase formal verification platform. The new system is designed for companies that wish to begin using formal verification on a small scale or those who need formal verification only a fraction of the time. By opening the door to possible savings in the order of hundreds of thousands of dollars, IBM is offering designers and verification engineers an affordable entry-point formal verification solution that can be used to introduce formal verification into their design methodology and gain a competitive advantage.

Hard-to-find bugs are often beyond the reach of conventional simulation technologies, which are traditionally used to find bugs in a design.

Formal verification tools enable validation experts to reach a level of design integrity otherwise unattainable using conventional approaches‹and at an early stage in the design cycle.

As a result, many companies are turning to mixed validation‹using formal verification together with simulation‹as the most efficient approach for their design cycle.

"Ultimately, using formal verification is an economic decision.

Until now, most companies invested in a formal verification platform only if a large portion of the design methodology required it," notes Dr Yaron Wolfsthal, Senior Manager of Formal Verification and Testing Technologies at the IBM Haifa Labs.

"This technology represents IBM's commitment to formal verification technology at all levels of design work."

The RuleBase family represents an industry-leading solution for the formal verification of complex microprocessors and ASICs.

Earlier this year, IBM announced the RuleBase Parallel Edition (PE), which enables engineers to rapidly verify complex chip designs by harnessing the power of parallel computing.

RuleBase SE verifies a logic design against a set of assertions that represent the desired behavior of the design.

The new system incorporates many of the RuleBase powerful static analysis algorithms‹without the high-end parallel formal verification technology intended for the largest possible design problems in leading-edge ASICs and microprocessors.

RuleBase SE runs on AIX, Solaris, and Linux and supports the standard property specification language PSL.

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