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The latest motherboard in the HAPS family gives customers access to multigigabit serial links, embedded PowerPC processors and more than 1600 pairs of LVDS signals.
The board, named HAPS-20, is targeted for designers who need high-speed prototypes of large ASICs.
'We are proud to announce what we believe to be the most advanced FPGA platform for ASIC prototyping today', stated Lars-Eric Lundgren, President and CEO of Hardi.
'Our customers are facing complexity and time-to-market pressures like never before'.
'Not only does our HAPS-20 keep pace with these challenges, but it offers even more functionality at as much as a 20% lower cost over the previous generation'.
'In addition, our customers are able to verify designs faster using our best-in-class connectivity and Lego-like flexibility'.
The HAPS-20 is carefully designed for maximum performance, with respect to signal integrity, speed and other critical issues.
The board can be used as a stand-alone device to prototype ASIC designs up to four million gates.
Capacity can be further increased by stacking two or more HAPS 20 boards together.
The HAPS-20 conforms to the HAPSTrak standard, which guarantees compatibility with previous and future generation HAPS motherboards and daughter boards (eg RAM, I/O, communication, connector boards etc).
The new board uses four Xilinx Virtex-II Pro XC2VP70/100 devices in the largest PIN count package, offering 80 multigigabit serial links, eight embedded PowerPC processors and over 3000 user I/Os.
All I/Os can be used in differential mode (LVDS), enabling long distance drive capability at transmission rates exceeding 800Mbit/s per channel.
More than 2000 interconnects between the FPGA devices make it ideal for large ASIC designs with wide buses.
The user I/Os are divided into three groups with separate power, which means that three different I/O voltages can be used at the same time.
Programming is done via a standard JT interface or from a CompactFlash memory.
As with all HAPS boards, the data programmed into the FPGAs can be encrypted by a battery-backed encryption key.
All necessary voltages are generated locally from a single external 5V source.
An onboard temperature watchdog and built-in self-tests are guarantees that the ASIC design is running on flawless hardware.
'HAPS-20 is a refinement of the HAPS-10 concept', stated Jonas Nilsson, Worldwide Technical Manager for HAPS.
'We've made I/O signalling more flexible with adjustable signal levels, and the switch to Virtex-II Pro devices not only gives access to multigigabit I/O but also makes prototyping faster'.
'HAPS 20 gives the designer more time to spend optimising the ASIC design rather than the FPGA board'.
HAPS customers get to verification faster by using off-the-shelf software for synthesis and debugging - including Synplicity's Certify for synthesis and Xilinx ChipScope, and Synplicity's Identify and Temento's DiaLite for real-time debugging.
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