Product category: Design and Development Software
News Release from: Hier Design | Subject: PlanAhead
Edited by the Electronicstalk Editorial Team on 10 September 2003
Floorplanning aids FPGA design
PlanAhead hierarchical floorplanning and analysis software from Hier Design offers full support for the latest version of the Xilinx Integrated Software Environment 6.1i (ISE)
The combination of ISE 6.1i and the PlanAhead software gives users of Xilinx Virtex-II and Spartan-3 device families an ASIC-like flow for the design of FPGAs. Customers benefit from a proven methodology for reducing place and route time, the number of design iterations, and the time needed to achieve timing requirements Hier Design provides advanced floorplanning and integrated analysis capabilities to identify and correct potential routing congestion, utilization, timing and other problems early in the design cycle, where they are easier and faster to fix.
Related stories
Floorplanner gains Java-based visualisation
Hier Design is to bundle Concept Engineering's NlviewJA Widget, a Java-based visual debugging software engine, into its PlanAhead hierarchical floorplanning and analysis software
Floorplanner helps FPGA designers to plan ahead
The PlanAhead hierarchical floorplanner is the heart of the new silicon virtual prototyping solution from Hier Design for high-end field programmable gate arrays (FPGAs)
"Tough the integration of ISE 6.1i and our PlanAhead software, FPGA designers have a tool flow that's virtually indistinguishable from an ASIC design flow, and get similar flexibility and productivity enhancements", remarks Salil Raje, Hier Design Chief Technology Officer.
The PlanAhead software shortens the design cycle by providing a faster, less iterative path from logic synthesis through physical design while reaching and maintaining design performance goals.
Its advanced analysis capability enables designers to more easily comprehend, modify, verify and implement their Xilinx FPGAs.
Further reading
FPGAs gain virtual prototyping support
Hier Design is to provide full support for Xilinx's new class of 90nm Spartan field programmable gate array solutions
"Hier Design's PlanAhead software provides a unique FPGA design solution which will help enable the further growth of the FPGA market,adds Jerry Banks, Director of Global Alliances at Xilinx.
"Our development groups have worked closely together to ensure the tightest possible integration and deliver a design flow with unmatched high-speed design capabilities and ease-of-use floorplanning features".
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