Encounter with new thermal analysis engine

A new design flow integrates Gradient's FireBolt thermal analysis engine into Cadence Design Systems' Encounter digital IC design platform.

A new design flow integrates Gradient's FireBolt thermal analysis engine into Cadence Design Systems' Encounter digital IC design platform.

This integration brings temperature awareness into the Cadence Encounter digital implementation tools.

Cadence Encounter customers can now use the FireBolt thermal analysis engine to analyse and minimise temperature gradients across a system-on-chip (SoC) or integrated circuit (IC) while preserving physical design constraints.

"Temperature behaviour has become a significant concern for designers at 65 nanometres", said Eric Filseth, Vice President of Marketing at Cadence.

"The need to analyse and repair critical problems caused by the effects of temperature within a chip plays an important role in achieving timing and power closure in next-generation design flows".

"Timing margins in particular can be minimised when temperature effects are accurately taken into account".

"Cadence commands a very large percentage of the physical design market, so we are especially pleased with our existing relationship with them", said Rajit Chandra, Gradient President and CEO.

"We look forward to helping our mutual customers achieve thermal integrity in conjunction with a market-leading platform such as Cadence Encounter".

At 90nm and below, designers cannot ignore temperature gradients, as they will cause design failures.

Power analysis captures discrete points of power consumption and power densities within the chip, but temperature is ultimately a function of power density, conductive properties of the materials, and boundary conditions within the chip and the package which power analysis is not able to provide.

Very often the maximum power or the maximum power density is not where the maximum temperature occurs, nor are the temperature gradients predictable by power analysis alone.

Customers using the integrated solution will be able to use Gradient's thermal analysis and repair engine at various levels of abstraction during the physical design of a semiconductor.

For example, floorplanning tools will use temperature results to place the blocks for least, or optimal thermal gradients; the power rail and clock signal will be analysed for IR drop, electromigration, and delays, respectively.

The thermal analysis function within the place and route tool will query cell moves that minimise the temperature gradients within the chip.

At the final routing stages, temperature data will be used for final analysis and sign off.

Appropriate repair techniques will be used at each level for optimising the thermal gradients.

After the final routing and temperature-aware timing analysis is completed, if there are any more hot spots, FireBolt will use thermal structures to further minimise temperature gradients, and the flow will then be completed with the optimal temperature distribution for the given design and package parameters.

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