Software provides full-chip temperature map in 3D

Gradient Design Automation reckons it has launched the first product in electronic design automation (EDA) history that brings temperature awareness to existing design flows for integrated circuits.

This week at the Design Automation Conference in Anaheim, Booth 1276, Gradient introduced FireBolt, a core thermal analysis engine that enables temperature awareness in industry-standard physical design tools that analyse leakage power, voltage (IR) drop, electromigration and timing of chips for portable devices, high-end graphics processors, automotive electronics, and memories such as DRAM and Flash.

Without temperature awareness, using these tools in 90nm and smaller technologies may result in large inaccuracies in their results due to on-die temperature variations.

"Thermal challenges arise from dynamic variability of chip parameters during the operation of a chip, and need to be made predictable and manageable like other DFM issues", said Rajit Chandra, Gradient founder, President and CEO.

"However, the temperature of a chip is deterministic for a given power density distribution; it does not make sense to take statistical approaches, as they can lead to over worst-casing and can mask real problems".

"Conforming to design specifications is important for our customers".

"They are faced with challenges during design, but also have to account for long-term reliability issues".

"We are providing tools that allow them to achieve these goals, and we are pleased to launch FireBolt into the market today", Chandra added.

FireBolt is the first and only product that provides a 3D full-chip temperature map to account for the electrical effects of thermal gradients within a semiconductor.

Loaded with innovative capabilities, FireBolt is the first EDA product to: capture 3D full-chip temperature variations; locate maximum temperature differences on the die due to device self-heating; provide leakage power analysis using computed temperatures of the devices; calculate metal temperatures due to wire self-heating (useful for accurate electro-migration rule checking); provide a list of devices and their locations based on temperature; provide a list of metal and interconnect temperatures; and provide "contour maps" for temperatures to help in hotspot removal.

The higher levels of integration and higher power density on today's chips are causing heat and temperature gradient problems that are not addressed by current methodologies.

Existing design tools typically use a constant temperature methodology and attempt to account for temperature variations by considering a large number of statistical temperature points.

The constant temperature approach is flawed in two ways.

First, each temperature datapoint assumes a constant on-chip temperature, and that is no longer a realistic assumption with small geometries.

Secondly, the statistical distribution is usually aimed at worst-case situations, which inhibits design optimisation due to the large design margins needed in such situations.

Because of these flaws, it is possible to miss a real temperature-related design violation that could cause leakage power, IR drop, timing closure and reliability problems.

Through thermal analysis, optimisation, and repair, Gradient technology and tools address these issues, reduce costly design margins, and avoid temperature-induced semiconductor failures.

"Gradient's technology is addressing a problem that is of increasing concern for many semiconductor companies using nanometre process technologies", said Jim Hogan, General Partner at Telos Ventures.

"Having spent more than a decade of my career worrying about the reliability of semiconductors in the field, I have a great appreciation for the significance of temperature gradients on design quality and reliability".

"Gradient's innovative and novel technology is equipping designers to consider temperature as part of the analysis process, so product life cycle issues can be addressed effectively in the design flow and not once in the field".

FireBolt is interoperable with the leading analysis and implementation flows and can be used at any point in the physical design process, even for hierarchical designs.

The new product is deterministic for a given power distribution and the factors that cause it to vary with temperature, and is fast enough to handle large, complex designs.

The use model is intended to support "what-if" analysis under several operational states.

FireBolt is available now on a time-based licence.

US pricing starts at $150,000.

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