Gradient stresses thermal integrity

Gradient Design Automation has revealed its strategy to deliver thermal integrity to integrated circuit designs for portable devices, high-end graphics processors, automotive electronics and memories.

Gradient Design Automation has revealed its strategy to deliver thermal integrity to integrated circuit designs for portable devices, high-end graphics processors, automotive electronics and memories such as DRAM and Flash.

The semiconductor market is trending towards higher levels of integration and higher power density on semiconductor chips, resulting in heat and temperature gradient problems.

These problems are not addressed by existing tools and methodologies, which assume a constant temperature throughout a chip, and as a result, leakage power, IR drop, timing problems and electromigration are causing chip failures.

"Design closure of modern semiconductor products can only be reached by using a temperature-aware design methodology throughout the design flow", said Rajit Chandra, founder, President and CEO of Gradient.

"Thermal analysis and thermal repair create thermal integrity, which is a necessary ingredient in nanometre chip designs".

Chandra added: "Our mission is to accurately compute all the temperatures on a chip, provide the data so physical designers can analyse it, and repair thermal problems before they cause a chip to fail".

According to the International Technology Roadmap for Semiconductors (ITRS), a knowledge deficit in heat and an absence of thermal tools will force chip designers to apply costly timing and power margins of 30% to 40%.

Actual measurements on designs have shown the existence of large temperature gradients within a chip, leading to inefficient timing optimisation and large timing errors.

Gradient's first product, FireBolt, is a core thermal analysis engine that computes chip temperatures and provides temperature data with analysis and repair capabilities to existing industry-standard physical design tools.

"Gradient products are essential for reaching thermal closure before tape-out and manufacturing of complex integrated circuits".

"Consequently, they can save many chips from failing when tested or even after their deployment in the field", said Dr Alberto Sangiovanni-Vincentelli, holder of the Buttner Chair of the Department of EECS at the University of California at Berkeley, a founder of Cadence and member of the Gradient Board of Directors.

"Heat is a serious problem at small geometries, and it's never constant across a chip - temperature and its variations impact everything from power consumption, performance, and reliability, to the yield and manufacturability of today's ICs".

Rajit Chandra, President and CEO, founded Gradient in 2003.

Dr Chandra was previously Vice President of Technology at Magma, and the founder of Moscape, which was acquired by Magma in 2000.

Previously, he was at Cadence, where he developed the Central Delay Calculator, and the industry standard delay format (SDF).

He began his career as a performance verification lead in the microprocessor design team at Intel Corporation.

Robert Johnson, Gradient Vice President of sales and Marketing, was formerly Executive Vice President at Barcelona Design and Vice President of Worldwide Sales at Tality.

The development team at Gradient includes a multidisciplinary team of experts in thermal modelling, computational geometry and EDA.

Gradient, headquartered in Santa Clara, California, received its Series A funding from Alloy Ventures, Cadence and Lanza TechVentures in November 2003.

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