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Product category: Intellectual Property Cores
News Release from: Gaisler Research
Edited by the Electronicstalk Editorial Team on 22 February 2007
Simulator to support IP cores
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Gaisler Research has begun working with Aldec, a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices.
Gaisler Research has begun working with Aldec, a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices The GRLIB IP core library from Gaisler Research is ideally suited for SoC designs and implements plug and play capabilities that minimise the engineering effort during the design phase