Multichannel multiprotocol access control chips

Exar has updated its DS3/E3 ATM UNI offerings with the introduction of a new family of low-power, highly integrated devices.

Exar has updated its DS3/E3 ATM UNI offerings with the introduction of a new family of low-power, highly integrated devices.

They combine E3 and DS3 speeds with ATM and PPP (point-to-point) protocol support in one device - this integration level is unique in the market.

Additionally, OEMs that design these new ATM UNIs with Exar's leading multichannel transceivers (XRT73L0x) can expect significant chip count reductions for many popular applications.

In three- and four-channel configurations, the XRT74L73/74 supports traditional ATM data transmission, and through PPP sustains IP packet processing for applications including access aggregation, digital cross connect switches, ATM WAN switches and network interface service units.

For ATM applications, the product series is compliant with 8/16bit Utopia Level I and II multi-PHY interface specifications.

The Utopia bus operates at 25, 33 or 50MHz.

It contains configurable on-chip FIFO (four or eight cells) in both the transmit and receive directions.

Also, it contains an on-chip 54byte transmit and receive OAM cell buffer for transmission, reception, and processing of OAM cells.

The devices support M13 and C-Bit parity framing formats for DS3 and ITU-T G.751 and ITU-T G.832 for E3.

Each device has a PRBS generator and receiver, and will interface to 8bit wide Intel, Motorola PowerPC and MIPS microprocessors.

Also, the devices have separately accessible external cell insertion/extraction buffers allowing cells to be added or removed from the data stream without going through the Utopia bus.

Four generic cell filters are provided to allow idle, OAM or data cells to be filtered in both the receive and transmit direction.

When running in PPP mode, the XRT74L7x provides checksum generation, byte stuffing and self-synchronous scrambling.

The multi-PHY interface will support either a slave mode or master mode.

Packet mode addressing is supported either in band or out of band.

The packet processor can be instructed to continuously process packets or stop after each one.

In addition to IP and ATM, these devices also support high-speed frame relay applications by configuring the embedded framer to operate in clear channel mode.

In addition, an HDLC capability is integrated with the framer.

The framers support the synchronous status requirement of ITU-T G.832_1998, which allows the system to monitor which frame is being processed by a particular framer.

Samples of both chips will be available in October 2001.

Both are offered in the 388-pin PBGA packages, supporting commercial and industrial temperature ranges.

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