News from: eASIC Corp
Edited by: Electronicstalk Editorial Team on 25 April 2005
Note: Readers of the Editor’s free weekly email newsletter will have read this news the week it was announced. . It’s free!
eASIC customer STMicroelectronics has achieved 24 hours turnaround from RTL to tapeout using the company's Structured eASIC technology.
ST has licensed eASIC's 0.13m eASICore for the rapid customisation of a printer platform, which allows ST to offer fast and easy customisation of a printer system controller, as well as image processing personalisation, in a standard preverified printer-engine architecture.
ST's engineering team was able to ship the final GDS-II files to the silicon fab for e-beam customisation in less than a day from the time RTL was received.
The e-beam customisation, which is maskless, takes only a few hours for Structured eASIC devices since just a single via layer needs to be written.
'In an ongoing effort to meet our customer's escalating needs, STMicroelectronics has developed programmable platforms and ASSPs that provide the required flexibility for new applications and configurability for printer products', said Vittorio Peduto, General Manager of Computer Systems Division at STMicroelectronics.
'Our goal is to obtain state-of-the-art design capabilities that make it easier for us to deliver leading-edge ICs, therefore we engaged with eASIC for its breakthrough configurable logic technology'.
'We benefited 24h design turn around time from RTL to tapeout'.
'With eASIC's technology we can make very efficient use of our direct-write e-beam equipment and eliminate the high cost of mask for customisation'.
'STMicroelectronics and eASIC achieved this industry milestone by working together to efficiently employ eASIC's configurable logic fabric within the printer platform chip', said Zvi Or-Bach, CEO and founder of eASIC Corp.
'We are delighted with our joint work with a technology leader like STMicroelectronics who has already recognised the tremendous potential and importance of direct-write e-beam'.
'This achievement demonstrates how a user of the eASIC configurable logic technology has been able to reach the goal of customising high density logic chips in a matter of days'.
'This new reality of rapid design with no NRE is becoming available for high end applications in the form of domain specific platforms by STMicroelectronics and for the main stream in the form of FlexASIC structured ASIC solution we are rolling out jointly with Flextronics Semiconductors'.
eASIC's innovative customisation technique enables eliminating multi-million-dollar mask sets cost using direct-write e-beam customisation approach for ICs.
Based on the company's breakthrough via-customisation technology, eASIC's fabric yields about ten times higher throughput of direct-write e-beam machines, compared with metal customisation.
This is made possible as vias occupy about 1% of the customisation layer area, whereas metal occupies at least 30% of the area, which impacts the direct-writing time and operation cost.
Moreover, as only a single via-layer is required for Structured eASIC customisation, it further shortens the turnaround time and eventually cuts the cost.
eASIC is the only company offering ASIC without NRE cost.
Although FPGAs do not require NRE either, their per-unit cost is dramatically higher than ASICs and their performance is lower by about an order of magnitude.
E-beam direct-write customisation is a preferred alternative for Structured eASIC prototyping and low volume while for higher volumes, a single via-mask is generated for the routing customisation.
No additional engineering efforts are required when moving to higher volumes, as the same GDSII files are used for the single via customisation with either e-beam or conventional lithography mask.
In order to complement the efficient interconnect routing with design flexibility advantages, the logic cells in the Structured eASIC fabric are customised with bit-stream and look-up-tables (LUTs), similar to FPGAs.
This unique combinations that employs different customisation techniques for routing and logic cells, creates an optimal Structured ASIC solution that provides ease-of-design together with low cost and high performance.
In addition, the bit-stream logic customisation allows for an easy post-fabrication debug and hence shorter time to market.
