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eASICR Corp has taped out its first structured ASIC array to be fabricated by a European IDM partner using 0.13-micron process technology. The taped-out array, called FA1, is the smallest member of the company's Structured eASIC product family. The initial parts will be used to characterise timing and power for the Structured ASIC fabric and cell libraries.
The complete product family is scheduled to be released for production in early Q1 2005.
This product is being codeveloped with Flextronics Semiconductor who will also be offering structured ASIC products and services.
"The structured ASIC evolved out of the need for a more flexible, less costly approach for completing medium-complexity ASIC designs in a more-timely manner to meet changing market conditions", said Rich Wawrzyniak, Senior Analyst, ASIC - SoC at Semico Research Corp.
"The rising costs and increasing design cycle times for standard cell and system-on-a-chip products has pushed many would-be users out of the market and forced them to explore other alternatives".
"The structured ASIC approach provides these would-be users with a welcome alternative".
"The direct-write e-beam approach employed by eASIC allows for an even lower manufacturing cost which enables even more would-be users to consider an ASIC solution once again and increases the potential market even more".
"Taping out our first structured ASIC device is an important milestone in our business strategy", said Zvi Or-Bach, eASIC President and CEO.
"This move, which was achieved through joint efforts with Flextronics Semiconductor, is a step forward along the path to offering innovative, NRE-free structured ASIC devices".
"There is a clear market need for alternative solutions to standard cell and a strong momentum is being built for structured ASICs".
"The combination of our patented technology with Flextronics' expertise and resources creates a very powerful solution that allows customers to significantly cut cost and shorten time-to-market of ASIC designs".
eASIC has developed a novel structured ASIC technology called Structured eASIC.
The patented Structured eASIC architecture consists of an array of logic cells (e-cells) with SRAM based LUTs (lookup tables) and flip-flops.
E-cells are interconnected by a segmented wiring grid using upper metal layers, which are customised per customer design with a single via-mask.
Logic programming of the e-cell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device.
Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom via-mask for customising the routing.
Moreover, single via-customisation is a perfect fit for an alternative lithography approach, namely the direct-write e-beam.
Using direct-write e-beam completely eliminates the customisation tooling cost, shortens time-to-market and adds manufacturing flexibility.
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