Product category: PCB Assembly Equipment and Tools
News Release from: DEK | Subject: DirEKt Ball Placement
Edited by the Electronicstalk Editorial Team on 27 November 2002
Inline technology aids wafer-level
processing
Neil MacRaild of DEK explains how back-end packaging processes and technology must become more flexible for manufacturers to produce today's advanced packages at commercial prices.
Packaging and interconnection have a crucial impact on how fully the power of today's deep-submicron silicon can be accessed and exploited Not only must packaging offer sufficient electrical performance, it must also deliver it at low cost if the cost advantages of deep submicron fabrication are to be maximised
This article was originally published on Electronicstalk on 15 Jul 2005 at 8.00am (UK)
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A variety of advanced process technologies developed by DEK offer significant performance and cost advantages for semiconductor packaging.
There is much current interest in chip scale packaging, defined as an encapsulation no more than 20% larger than the chip itself.
One of the most popular is the wafer level CSP, or WL-CSP; solder bumps are deposited directly onto ohmic contacts on the silicon wafer before the assembly is reflowed to create a firm mechanical and electrical interface ready for placement of the component in an automated surface mount assembly environment.
The package eliminates the gold bond wires that traditionally make the connection between the die and a separate lead frame.
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The solder bumps may be deposited on the wafer surface as pre-formed solder balls or as bricks of solder paste.
There are several ways to achieve this, and one of the challenges facing developers of WL-CSP and other flip chip techniques is to deliver the package advantages in a process that is compatible with high volume manufacturing.
Wafer bumping can be achieved using sputtering or e