Product category: Microprocessors, Microcontrollers and DSPs
News Release from: ChipX | Subject: Embedded arrays
Edited by the Electronicstalk Editorial Team on 12 February 2007

Embedded arrays are novel ASIC option

Embedded arrays are based on configurable logic combined with standard cell I/O and memory structures, optional mixed-signal IP, all matched exactly to application needs

Leveraging the company's expertise in structured ASICs, ChipX is introducing today embedded array products built with structured ASIC libraries, also know as a 'structured ASIC fabric'. The first family to become available is built using UMC 0.13um high-speed (HS) process. Embedded arrays add an exciting new option to the products that ChipX customers can use to bring their ASIC to market.

To date, most options available to ASIC designers were either based on a fully customised product (Standard Cell), or on the fully configurable structured ASIC as pioneered by ChipX.

'With the time of developing Standard Cell ASICs in advanced processes getting longer and costing in the tens of millions of dollars, companies cannot afford to make mistakes'.

'Further, the ability to develop derivative products, no matter how small the changes are, is also an expensive and time consuming undertaking that many companies are sometimes forced to eliminate', said Elie Massabki, Vice President of Marketing at ChipX.

'In price sensitive markets, companies need to reach the lowest cost solution as quickly as possible in order to gain acceptance and win market share'.

'Embedded arrays are designed to address and offer a compelling solution for all these problems'.

Although standard cell ASICs offer the closest design fit, and hence the best part price, the ability to make big design changes quickly is virtually impossible.

Derivative products take just as long to build as the original product and cost just as much.

Whilst it is possible to make minor metal layer changes in standard cell, thereby avoiding full respin costs, such changes typically require substantial manual routing skill increasing implementation risk.

Structured ASICs can be implemented in a fraction of the time and upfront cost as standard cell ASICs.

The ability of structured ASICs to change the entire design without requiring a new mask set does mean the customer pays a small penalty in device size.

Also, the level of integration with mixed signal IP and the exact customer's configuration may not be available in a structured ASIC.

ASIC designers who require more flexibility to fix or amend their product than a standard-cell-based ASIC, and requiring immediate aggressive volume production pricing, can now benefit from embedded array technology from ChipX.

ChipX embedded arrays are based on the company's patented X-Cell configurable logic combined with standard cell I/O and memory structures, optional mixed-signal IP, all matched exactly to the application needs.

As a result, designers can make substantial logic changes, corrections or additions to the device using a completely standard automated tool flow.

Respins or logic feature changes can therefore be implemented significantly faster, more cost effectively, and with much lower risk than manually inserted changes to metal layer masks.

Such additions can be completed in as few as six weeks, a sharp contrast with a full standard cell device respin requiring a minimum of 12 weeks and potentially a full mask set.

Because almost all building blocks used in a ChipX embedded array are from standard cell libraries, performance of the complete component is very similar to standard cell, both in terms of power and maximum speed.

Achievable logic speeds are typically less than 10% below standard cell performance, in the same process.

ChipX Embedded Array in 0.13um HS is available for designs starting today.

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