Product category: Intellectual Property Cores
News Release from: CebaTech
Edited by the Electronicstalk Editorial Team on 18 July 2006
Strategy centres on IP
IP and ESL technology
CebaTech has unveiled its strategy to deliver high-value, high-performance Internet Protocol intellectual property and breakthrough ESL technology to companies developing ASIC and FPGA solutions
CebaTech has unveiled its strategy to deliver high-value, high-performance Internet Protocol intellectual property and breakthrough electronic system level (ESL) technology to companies developing ASIC and FPGA solutions. The company is targeting developers in the communication, networking and storage industries as well as in the broader integrated circuit (IC) and software communities that seek to leverage existing investments in open source and proprietary C source code.
This article was originally published on Electronicstalk on 18 July 2006 at 8.00am (UK)
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CebaTech makes it possible for IC design teams to take a software-centric approach to hardware design.
Using CebaTech's solutions, designers can generate correct embodiments of register transfer level (RTL) hardware derived from working and verified software, effectively eliminating the need for RTL simulation, the IC verification bottleneck.
CebaTech was founded in 2004 by a team of technology and business professionals, with over 20 years experience working together.
The team has experience in IC design, EDA, communication systems, storage design, and manufacturing in large and small corporations, including IBM, Lucent, Nortel, Intel, 3Com, Ansoft, Connectware and Sandgate Technologies.
CebaTech's Internet Protocol intellectual property cores and aggressive software-centric ESL chip design methodology come from the team's wealth of domain expertise in developing high-performance ASIC solutions for networking and from its thorough understanding of the challenges and risks of hardware development.
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CebaTech's ESL technology enables an entire system-on-chip (SoC) to be coded in C and run in a native C software environment, where running the tool-generated cycle-accurate C will precisely represent the behaviour of the generated RTL running in an HDL simulator.
'CebaTech's deep knowledge of IC design and software development allowed them to develop a new design approach as design complexity has increased'.
'The company's approach to turning software into silicon has been used internally to produce a TCP/IP engine that was licensed to a major semiconductor company'.
'Few start-ups have validated their approach so thoroughly before they even launch their first product'.
said Steven Leeke, Partner, 2M Companies CebaTech's first intellectual property blocks have been identified as a set of communication protocols derived from open source code.
These communication protocols will scale from 1 to 10Gbit/s and will simplify and speed to market a new generation of storage, security and networking products.
'CebaTech technology allows developers to make a radical advance in hardware development and to solve previously intractable problems in functional design verification', said Tim Sullivan, founder and CEO, CebaTech.
'By delivering intellectual property blocks that can be dropped into place by hardware developers, we eliminate the need for these developers to create RTL implementations of highly complex protocols- a tremendous boost to design teams in terms of man-power resources and time required to implement SoCs'.
As CebaTech IP blocks are tremendously more complex than the traditional intellectual property blocks used in the FPGA or ASIC industries, the company developed a compiler/ electronic design automation (EDA) toolset that creates synthesisable RTL for integrated circuits (ICs) from C source code.
'Verification has become the major bottleneck in IC development'.
'It takes too much time and costs too much money to verify hardware designs in an RTL simulator'.
'CebaTech's innovative approach-development of designs using untimed C, verification in a native C environment, and then compilation of the C code to cycle-accurate C (CAC) for cycle-accurate verification in the same C environment - will enable a huge reduction in verification time; eliminate RTL simulation from the development phase; and eliminate re-spins due to inadequate verification coverage', said Chad Spackman, CTO, CebaTech.
'Our flow allows engineers to create new chip designs on a dramatically shortened timescale, with significant increases in reliability, higher performance and lower cost of silicon'.
Using C as a programming language for high-level, complex IC design, CebaTech intends to drive the adoption of ESL/top-down design and to revolutionise IC design by dramatically shortening the time to market for deployment of chip-based products that embed complex protocols.
Under the direction of hardware architects, this allows compilation of existing, tested, software directly into hardware, eliminating many of the requirements to write specifications and test benches and manually translate code from existing C implementations into hardware-based (RTL) state machines.
The strategy enables functional testing in native C software environments, executing hundreds of millions of instructions per second, compared with the industry-standard RTL simulation approach, where typically a week or more of machine time is used to perform one second of simulated time.
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