Product category: Power Supply ICs and Controllers
News Release from: Catalyst Semiconductor
Edited by the Electronicstalk Editorial Team on 19 June 2003
Patent award for novel LDO design
Catalyst Semiconductor has been awarded a US patent on its innovative, low dropout linear voltage regulator design
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Catalyst Semiconductor has been awarded a US patent on its innovative, low dropout (LDO) linear voltage regulator design. The new circuit technique enhances Catalyst's capability to incorporate its programmable EEPROM technology and mixed-signal design into system level ICs. "This patent grant is an important milestone in Catalyst's movement toward system-level ICs that combine our extensive EEPROM capability with mixed-signal circuits", said Barry Wiley, Vice President of Marketing for Catalyst Semiconductor.
"We believe exploiting this capability will allow us to make key contributions to our existing mobile communication, automotive and consumer electronic customer base".
US Patent 6,518,737 covers a low dropout (LDO) linear regulator with non-Miller frequency compensation.
Optimum frequency compensation and transient response are obtained by using wideband, low-power operational transconductance amplifiers (OTAs).
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In contrast to previous approaches, requiring tightly specified equivalent series resistance (ESR) for the external capacitor, the patented solution imposes no lower ESR limit.
An LDO using a low ESR load capacitor will exhibit superior transient response with less undershoot or overshoot.
The transient response of the patented LDO very nearly resembles the response of a single-pole system.
The inventors were Cornel Stanescu of Bucharest, Romania, and Radu Iacob of Sunnyvale, California, both employees of Catalyst Semiconductor.
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