Cadence introduces Palladium XP computing platform

Cadence Design Systems has released the Palladium XP fully integrated verification computing platform, which unifies simulation, acceleration and emulation into a single verification environment.

Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better-quality embedded systems in a shorter time.

Cadence Palladium XP supports design configurations of up to two billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously.

The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.

The Palladium XP verification computing platform gives developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better-quality IP, subsystems and SoCs.

Design teams can 'hot swap' simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.

The Palladium XP verification computing platform is available in two configurations: XL for design teams and GXL for enterprise-class global teams.

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