Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Low-Power Solution
Edited by the Electronicstalk Editorial Team on 31 January 2007
Mobile audio chip cuts
power and boots first time
Silicon and Software Systems has achieved record-breaking production success using its low-power SoC design flow based on the Cadence Low-Power Solution
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The Cadence Low-Power Solution is billed as the industry's first fully integrated flow for logic design, verification and implementation of low-power chips
Silicon and Software Systems (S3) has achieved record-breaking production success for a chip designed at its facilities using its nanoflowLP low-power SoC design flow based on the Cadence Low-Power Solution. S3 used a range of low-power design techniques such as multi-Vt libraries, power islands, power estimation and low-power verification for this chip, intended for mobile audio applications.
The chip booted correctly the first time in a portable computer application within 24 hours of wafers arriving from the foundry and consumed only 85% of the original power budget target set by the customer.
The Cadence Low-Power Solution integrates leading-edge design, verification, and implementation technology with the Si2 Common Power Format (CPF), a standardised format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers.
By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, greatly reduces power-related chip failure, and provides power predictability early in the design process.
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This holistic approach to addressing the low-power challenge is necessary for managing power consumption in 90 and 65nm designs.
'With the Cadence Low-Power Solution we were able to optimise our nanoflowLP and leverage our strong engineering expertise and experience', said Dermot Barry, General Manager, System IC Business Unit, S3.
'As a result, our customers achieve right-first-time silicon and reduced time to revenue'.
'With the latest low-power optimised flow from Cadence we can now meet the high expectations of our customers'.
'We applaud S3's ability to deliver another customer success based on our extensive low-power flow-development partnership'.
'The exciting technology advancement by the Cadence Low-Power Solution, based on the Common Power Format, brings a new level of automation to the ever challenging low-power designs at deep submicron nodes', said Dr Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward at Cadence.
'S3's ability to incorporate the latest low-power techniques and deliver fast turn-around times means that lowest cost SoCs can be achieved with minimal risk or compromise on performance'.
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