Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Low-Power Solution
Edited by the Electronicstalk Editorial Team on 30 January 2007
Software preserves low-power design
intent
The Cadence Low-Power Solution is billed as the industry's first fully integrated flow for logic design, verification and implementation of low-power chips.
The Cadence Low-Power Solution is billed as the industry's first fully integrated flow for logic design, verification, and implementation of low-power chips The Cadence Low-Power Solution integrates leading-edge design, verification, and implementation technology with the Common Power Format (CPF), an Si2 format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers
This article was originally published on Electronicstalk on 31 Jan 2007 at 8.00am (UK)
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By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, reduces power-related chip failure, and provides power predictability early in the design process.
"This is a dramatic step forward for designers seeking low-power design capabilities", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"This solution is the first to provide designers with the ability to automatically instantiate low-power techniques at the register-transfer level (RTL) using a common format, with the assurance that they will function correctly throughout the verification, front-end implementation and physical-implementation steps".