Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 16 March 2006
IEEE recognises SystemVerilog development work
Nine Cadence technologists have received IEEE awards for a wide range of improvements during the development of the SystemVerilog standard
The IEEE has recognised Cadence for its leadership and contributions to the IEEE1800 SystemVerilog standard. Nine Cadence technologists received awards for a wide range of improvements during the development of the SystemVerilog standard. The Chairman's Award went to Vassilios Gerousis and Francoise Martinolle.
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Gerousis was recognised for architecting the combination of HVL and HDL and driving it from conception to reality.
Martinolle was recognised as one of the SystemVerilog champions leading the resolution of many issues among the various technical committees.
Certificates of Recognition were awarded to Victor Berman, Charles Dawson, Steven Dovich, Jay Lawrence, Kathy McKinley, Steven Sharp and Jim Vellenga, who chaired or served on several special task forces and committees.
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'The IEEE1800 SystemVerilog Working Group is pleased to recognise Cadence leadership and contributions', said Johny Srouji, Chair of the IEEE1800 SystemVerilog Working Group.
'The quality of the SystemVerilog language was significantly improved by Cadence's work and experience delivering standards'.
'We at Cadence are very gratified to have the opportunity to work with and contribute to the IEEE1800 standard', said Ted Vucurevich, Senior Vice President and Chief Technology Officer at Cadence.
'This activity - as well as our work with the IEEE p1647 e, IEEE1666 SystemC, IEEE1364 Verilog and IEEE1076 standards committees is invaluable to the interoperability that speeds products from plan to closure throughout the electronics industry'.
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