Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso RET Suite
Edited by the Electronicstalk Editorial Team on 14 February 2006
Suite makes IC designs more manufacturable
The Cadence Virtuoso Resolution Enhancement Technology (RET) Suite integrates lithography awareness directly into the Cadence Virtuoso custom design platform.
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The Cadence Virtuoso resolution enhancement Technology (RET) Suite integrates lithography awareness directly into the Cadence Virtuoso custom design platform, the leading design environment for custom ICs. With the Virtuoso RET Suite, designers targeting sub90-nanometre manufacturing technologies are now able to create layout designs that are less sensitive to critical yield-degrading lithography issues, and which are desensitised to common lithography-process variations. The Virtuoso RET Suite allows designers to analyse and optimise designs for both performance and yield by examining precisely how target layout structures will appear in silicon.
This is done by precisely modelling the distortions that are inherent in today's subwavelength lithography.
The suite includes interactive model-based simulation of layout designs, batch and interactive lithography rule checking, lithography-yield analysis and optimisation, and trial-based optical-proximity-correction (OPC) capabilities utilising critical lithographic parameters, including illumination mode, exposure and focus.
'We are pleased to adopt the Virtuoso RET Suite for use on our advanced DRAM memory processes', stated Takao Adachi, Officer, CTO, Technology and Development Office at Elpida Memory.
'As a leading memory manufacturer, optimising our designs for lithography accuracy addresses critical concerns by improving manufacturing precision and yield'.
'We look forward to Cadence continuing to develop and provide solutions that enable lithography-aware designs to avoid costly and time-consuming respins'.
The Virtuoso RET Suite is based on technology developed through Cadence's previously announced developmental agreement with ASML, the world's leading provider of lithography systems for the semiconductor industry.
With its tight integration into the Virtuoso environment, the Virtuoso RET Suite offers the same, familiar and intuitive user interface and use model that most layout designers routinely use today, thereby promoting easy adoption.
Dr Marc Levitt, Vice President for Design for Manufacturing (DFM) at Cadence, said: 'The Virtuoso RET Suite graphically illustrates our strategy of putting the 'Design' back into 'DFM.' Traditional post-processing DFM solutions have proven insufficient to address the demanding requirements of the most advanced semiconductor lithography and manufacturing'.
'Creating high-yield, high-performance designs requires that layout designers be aware of manufacturing effects'.
'The Virtuoso RET Suite directly addresses this need by allowing layout designers to see exactly what the resulting silicon will look like when manufacturing effects are considered'.
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