Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 9 February 2006
Award recognises new
approach to IC design
The Cadence X Architecture design solution has won the International Engineering Consortium DesignVision award for ASIC and IC Design Tools at DesignCon 2006
The Cadence X Architecture design solution has won the International Engineering Consortium (IEC) DesignVision award for ASIC and IC Design Tools at DesignCon 2006. The Cadence X Architecture design solution is the industry's first IC physical implementation system enabling designers to implement chips using the innovative X Architecture.
This article was originally published on Electronicstalk on 9 February 2006 at 8.00am (UK)
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The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle 'Manhattan' routes.
The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly reduced wirelength and fewer vias (the connectors between wiring layers).
'We are honoured that the IEC selected the Cadence X Architecture design solution as the winning entry in this very competitive category', said Kalyan Thumaty, Vice President and General Manager of X Architecture at Cadence.
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'The Cadence X Architecture design solution provides the industry with a revolutionary new way to optimise IC design cost, performance and power consumption for today's challenging market needs, making it an ideal solution for consumer, wireless and graphics market segments'.
'The DesignVision award is further validation of our commitment to innovation and focus on end-user needs'.
The Cadence X Architecture design solution enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow.
While leveraging Cadence's industry-proven Manhattan implementation expertise, the solution draws on innovations in placement, routing, infrastructure and extraction technologies.
ATI Technologies and Toshiba Corporation have successfully leveraged the Cadence X Architecture design solution and enjoyed its compelling benefits.
ATI implemented a high-performance, high-volume PCI-Express graphics processor using the Cadence X Architecture design solution and manufactured it using the TSMC 0.11-micron process.
This enabled them to eliminate one metal layer from the design, reducing the device's die cost.
Toshiba's chip, TC90400XBG, designed for integration in digital-media and home-entertainment applications, was fabricated using 130-nanometre process technology and is approximately 11% faster in speed and 10% smaller in random logic area compared with equivalent Toshiba products with the conventional 'Manhattan' design.
Foundry leaders TSMC and UMC provide production support for the manufacture of chips implemented using the X Architecture.
TSMC is production-ready for 0.13-micron, 0.11-micron and 90nm process nodes.
UMC accepts X Architecture designs for fabrication at 130 and 90nm process nodes.
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