Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Enterprise Specman Elite 5.0
Edited by the Electronicstalk Editorial Team on 22 December 2005
Testbench automation upgrades verification
The Cadence Incisive Enterprise Specman Elite 5.0 testbench automation solution features tight integration to the Incisive Enterprise Specman Simulator
Cadence Design Systems has made a major upgrade to its market-leading SoC verification technology with the release of the Cadence Incisive Enterprise Specman Elite 5.0 testbench automation solution with tight integration to the Incisive Enterprise Specman Simulator. Developed to serve multiple specialists, Specman Elite 5.0 provides up to three times greater run time and 60% greater memory performance than previous versions, with enhanced usability and improved scalability of generation and coverage.
This article was originally published on Electronicstalk on 22 December 2005 at 8.00am (UK)
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With the addition of 64bit support for the Intel EM64T and AMD Opteron platforms with RHEL 3 or SuSE 9 Linux, Specman 5.0 now addresses the growing demand for larger memory footprint capabilities that cover simulations run in full-chip and system-level verification.
It also provides the following improved functionality: enhanced full-system transaction modelling support with advanced options for connecting the testbench and design under test (DUT) to improve performance and code reusability; an improved user interface that simplifies the debug process; convenient new generation control capabilities with enhanced SystemC support that eases environment bring-up; improved coverage capabilities combined with multichannel sequence support, and TCM runtime optimisation, that enhances performance and overall 'coverage-driven verification' capabilities, critical for reducing quality risks and meeting project schedules; and advanced module to system-level techniques like reuse and built-in metrics based on the Incisive Enterprise plan-to-closure methodology.
'Specman has long been an essential part of our overall verification process', said Dr Andreas Dieckmann, Verification Manager, Siemens A and D.
'The combined new product adds the capabilities we need to scale and manage our overall verification process to address the growing complexity and complete SoC verification'.
'Our Incisive Enterprise verification solutions already offer the highest verification power in the industry', said Moshe Gavrielov, Executive Vice President of the Cadence Verification Division.
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'With this announcement, we have further distanced ourselves from the competition and delivered the next level of verification power that the most challenging next-generation SoCs will require'.
Enterprise Specman Elite 5.0 enables users to improve the quality of their end products while further shortening the entire verification cycle.
The underlying technology is at the core of Cadence's recently announced Incisive Enterprise family, and the corresponding plan-to-closure methodology designed to support enterprise-level verification process automation (VPA).
Incisive Enterprise targets the exponentially increasing complexity of the verification process associated with the integration of multiple specialists spanning block, chip and system-level verification of SoCs and hardware-software systems.
Incisive Enterprise Specman 5.0 and the Incisive Enterprise Specman Simulator are currently available as stand-alone products as part of the Incisive Enterprise product family.
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