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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: SoC Encounter GXL
Edited by the Electronicstalk Editorial Team on 6 December 2005

IC design platform adds yield analysis

Cadence Design Systems has released SoC Encounter GXL, completing its Cadence Encounter digital IC design platform product segmentation strategy

SoC Encounter GXL adds yield as a standard design target throughout the implementation flow to address both the 'defect' and 'process variation' challenges of advanced designs at 65nm and beyond. SoC Encounter GXL addresses nanometre defect yield issues with new yield analysis and optimisation capabilities embedded across the implementation flow.

For yield analysis, a new command, ReportYield, assesses full-chip or block-level defect yield losses based on factors such as critical area and cell yields.

A unique yield prototyping capability enables users to choose full-chip floorplanning strategies with visibility of yield considerations before committing to a physical architecture for the chip.

'Yield analysis and optimisation during implementation is critical for maximising design yield, especially at 65nm and beyond', said Satoshi Andou, General Manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu.

'With Encounter GXL, we are now able to analyse and improve yield at any point in the design flow and evaluate the impact of various design decisions, without leaving the Encounter platform'.

'Encounter GXL gives us the confidence that our yield-aware design will correlate to final silicon'.

For yield optimisation, SoC Encounter GXL supports cell optimisation in global RTL and physical synthesis using yield-aware cell libraries in either PDF Solutions' pDFm or a new Encounter format.

For interconnect optimisation, SoC Encounter GXL controls double via insertion, wire spacing and other factors concurrently during routing, instead of as a post processing step.

'Yield-aware physical synthesis is one of the highest-impact ways a design team can address chip yields', said Kevin MacLean, Vice President of DFM at PDF Solutions.

'Using SoC Encounter GXL with PDF Solutions'.pdfm files and pDfx- compliant libraries makes it possible for designers to easily produce more manufacturable SoC designs without compromise in other areas like schedule, timing and power'.

'The correct choice of library cells can have a significant effect on production yields at 90nm and below', said Brani Buric, Senior Director of Platform Product Marketing and Business Development for Virage Logic.

'Virage Logic's ASAP logic standard cell libraries with yield views will be available for use with SoC Encounter GXL on the Chartered Semiconductor 90nm process in Q1 2006'.

SoC Encounter GXL incorporates analysis and optimisation capabilities to manage the effects of nanometre process variation on design performance.

This includes a new multimode timing capability to reduce the complexity of timing optimisation in designs with multiple operating modes, increasingly common in low power and consumer designs.

Cadence plans to add a concurrent multicorner analysis and optimisation function in the first half of 2006, with statistical timing under development and scheduled for release in the second half of 2006.

SoC Encounter GXL also reduces overall design variation by reducing clock variation.

Leveraging advanced 'mesh' techniques traditionally used in high-performance microprocessors, SoC Encounter GXL automatically synthesises clock circuits with ultralow susceptibility to process variation.

On a high-performance communications design taped out in October 2005, an SoC Encounter GXL clock mesh provided an estimated 50% reduction in overall on-chip timing variation.

'Below 130nm, precision clock design is critical to control hold time and skew variation over process, and across the entire design simultaneously', said Kun-Cheng Wu, Director of Design Development at Faraday Technology.

'We are pleased with SoC Encounter GXL's clock mesh synthesis'.

'With it, we have been able to quickly produce low-skew, low-variation clock structures which reach aggressive constraints'.

'Controlling defect- and variation-related yields is a top consideration of designers ramping to advanced process technologies', said Wei-Jin Dai, Corporate Vice President, R and D for Cadence.

'High-end development teams now expect the design phase to help solve this problem; not only through EDA analysis and optimisation, but also through new circuit-design techniques and closer integration with manufacturing'.

'With SoC Encounter GXL, we deliver this in an easily adoptable form to facilitate the next generation of SoC complexity and help put the Design in design-for-yield'.

'In 1H06, we plan to introduce new DFM technology developed under Cadence's 'Catena' incubation project that will continue to meet these challenges'.

'As time-to-market windows continue to shrink along with process geometries, the emphasis on making informed design choices to speed yield ramp intensifies', said Walter Ng, Senior Director of Platform Alliances at Chartered Semiconductor Manufacturing.

'Bringing critical, calibrated manufacturing information into design requires close collaboration between semiconductor, IP and EDA companies'.

'Chartered and Cadence are actively driving solutions, including SoC Encounter GXL, to help address those challenges facing leading-edge SoC designers'.

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