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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: X Architecture design solutions
Edited by the Electronicstalk Editorial Team on 15 June 2005

Graphics processor shows
off X Architecture

ATI Technologies, Cadence Design Systems and TSMC have successfully produced the foundry industry's first X Architecture device

ATI Technologies, Cadence Design Systems and Taiwan semiconductor manufacturing Company (TSMC) have successfully produced the foundry industry's first X Architecture device. The ATI chip is a high-performance, high-volume PCI-Express graphics processor designed for desktop and notebook computers.

The X Architecture is a revolutionary new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption.

The ATI device was implemented using the Cadence X Architecture design solution and manufactured using TSMC's 0.11-micron process.

This implementation eliminated one metal layer from the original Manhattan design, reducing die costs.

The new device is expected to enter volume production late in the year.

'The X Architecture opens up a host of new possibilities for innovation in chip design', said Greg Buchner, Vice President of Engineering at ATI.

'As the industry leader in advanced graphics and digital media processors, ATI has long been a pioneer in adopting new chip design technologies'.

'Using the Cadence X Architecture design solution, we have been able to increase the performance envelope while reducing costs, providing new opportunities and possibilities within our PC and consumer businesses'.

'Our multi-year collaboration with Cadence has yielded tangible results'.

'We became the first foundry to develop X Architecture design rules'.

'Today, we are in early engagement with customers on 90-nanometre X Architecture designs and are currently developing 65-nanometre X Architecture design rules', said Dr Ping Yang, TSMC Vice President, R and D.

'ATI's chip validates TSMC's production-readiness of the X Architecture as a viable design alternative'.

The Cadence X Architecture design solution is the industry's first physical design solution that enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow.

While leveraging Cadence's industry-proven expertise in the Manhattan implementation, the solution draws on innovations in placement, routing, infrastructure and extraction technologies.

Cadence X Architecture design solutions for TSMC's 0.13-micron and 0.11-micron process nodes are now available to select customers under Cadence's value-based business model.

'Cadence is committed to providing inventive solutions for our customers' market success', said Kalyan Thumaty, Vice President and General Manager of X Architecture, at Cadence.

'We're excited to see that the technological innovations employed in the Cadence X Architecture design solution are enabling industry leaders such as ATI to meet challenging market requirements'.

'The collaboration between ATI, Cadence and TSMC has produced compelling benefits and validated the production-readiness of our X Architecture design solution'.

To bring the X Architecture into manufacturing reality, TSMC created extensive test structures to formulate competitive X Architecture design rules and developed a unique OPC model and mask making techniques.

TSMC also created enhanced technology files to handle diagonal design rules and parasitic extraction.

In recognition of this successful design chain collaboration in delivering this design, ATI is joining the X Initiative, and becomes the first fabless chip design member company.

'We're elated to welcome ATI, the world's leading graphics chip maker, as the first fabless member of the X Initiative', said Aki Fujimura, X Initiative steering group member, the co-inventor of X Architecture and Chief Technology Officer, New Business Incubation, at Cadence.

'The fabrication of ATI's chip by TSMC caps our efforts to ready the global semiconductor supply chain for production of fabless chips using the X Architecture'.

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