Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 1 March 2005
Library views improve signal-integrity analysis
Cadence Design Systems and Virage Logic Corp have released results of a collaborative project to provide library views to better address low-power, multiple-voltage nanometre design needs
Virage Logic has generated and qualified timing library views that include the Cadence effective current source model (ECSM) extensions for accurate supply-voltage delay prediction and noise library views (cdB) for signal-integrity (SI) analysis. When used with the Cadence Encounter digital IC design platform, these new library views enable design teams to accurately account for crosstalk, supply-voltage (IR) drop, voltage and frequency scaling, and multiple voltage-island support required for advanced nanometre technologies.
This article was originally published on Electronicstalk on 1 March 2005 at 8.00am (UK)
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In a single, integrated platform, Virage Logics IPrima Mobile includes single- and dual-port STAR SRAMs, Area, Speed and Power (ASAP) Memory ultra-low-power memories, ASAP Logic ultra-low-power standard cell libraries, and base I/O cells.
Support for cdB is included in the ASAP Logic standard cell products, and the ASAP Memory embedded memory compilers have been enhanced to enable noise-library creation (cdB).
This is essential to accurately isolate and correct crosstalk-induced failures that may occur at the interface to each memory block.
'Our customers demand fast timing closure when they take our synthesisable cores to silicon', said Tom Chanak, CAD Manager at MIPS Technologies.
'At high frequencies, SI has become a critical variable that needs to be built into any hardening flow'.
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'Having SI library views readily available allows us to get the best out of Cadence Encounter's automatic SI closure flow, enabling our customers to get to market faster'.
'ECSM models provide the accuracy and flexibility needed for our IPrima Mobile semiconductor intellectual property (IP) platform for low-power design', said Brani Buric, Senior Director of Product Marketing at Virage Logic.
'The accuracy of current source models such as ECSM influenced us to support this modelling approach to address the complex features of nanometre designs'.
'In addition, we worked closely with Cadence to generate and validate the noise models'.
'Virage Logic joins the growing list of leading IP providers that have adopted ECSM, making it the new de facto standard for nanometre delay modelling', said Jan Willis, Senior Vice President, Industry Alliances, at Cadence.
'By enabling designers to detect and repair SI problems earlier in the design process, they now can bring their designs to market faster, which is critical in today's competitive marketplace'.
For low-power applications that vary the supply voltage for a more effective tradeoff between performance and power, these new library views are essential.
The ECSM extensions to the timing libraries enable accurate prediction of performance at different voltage levels, including accounting for IR drop, while the noise libraries (cdB) permit accurate analysis of the combined impact of IR drop and crosstalk on functionality.
These views are especially important for low-power designs that use multithreshold cells and multiple power supplies and are consequently more sensitive to SI-induced failures.
The new library views are also available for nanometre timing and SI signoff with the Cadence CeltIC crosstalk analyser and the SignalStorm NDC nanometre delay calculator.
Created for the portable and hand-held market, the IPrima Mobile semiconductor IP platform provides several static and dynamic power saving features all designed to extend the battery life while maximising performance by reducing up to 20x static and 80% dynamic power dissipation.
IPrima Mobile builds on Virage Logic's three-plus years of silicon-proven experience in thousands of high-volume consumer products to provide SoC designers with a single, integrated IP platform that enables them to efficiently develop consumer products with longer battery life.
cdB noise model support is available with recent releases of ASAP Logic Standard Cell Libraries and ASAP Memory Compilers.
ECSM model support will be available in certain IPrima IP components starting in the second half of 2005.
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