Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 1 March 2005
GUC encounters tape-out success
The Cadence Encounter digital IC design platform has helped GUC successfully tape out seven 130-nanometre designs
With Cadence Encounter technology, GUC minimised design implementation time and achieved first-pass silicon success. The designs were developed for a variety of applications, ranging from WLAN, video and handheld devices, to networking and communications. The most sophisticated designs - with 3 million gates and 400MHz clock speed - were successfully closed with all timing and signal integrity requirements met.
This article was originally published on Electronicstalk on 1 March 2005 at 8.00am (UK)
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With much of the region still at 0.18 micron or larger process nodes, GUC is pioneering 130-nanometre design in Taiwan.
'We believe we are the first company in Taiwan to execute multiple tapeouts at 130 nanometres or below', said Jim Lai, President and COO at GUC.
'Through our tapeout successes, we have demonstrated that Taiwanese companies are capable of doing leading-edge digital designs'.
'Encounter is a viable and production-proven world-class technology that continues to deliver the fastest route to silicon for both mainstream and advanced process technology nodes'.
'We are pleased that the speed, capacity and maturity of the Encounter platform provided GUC with the productivity gains that allowed GUC to achieve so many successful tapeouts on schedule', said Wei-Jin Dai, Platform Vice President, Digital IC Implementation at Cadence.
'With continued customer successes such as this, the Encounter platform further extends its lead in digital IC implementation'.
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