Click on the advert above to visit the company web site

Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter Conformal Constraint Designer
Edited by the Electronicstalk Editorial Team on 18 January 2005

Software keeps track
of design constraints

Encounter Conformal Constraint Designer automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist

Available now from Cadence Design Systems, Encounter Conformal Constraint Designer automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist. The new product performs comprehensive design constraint quality checks to ensure that designers start with high-quality constraints up front.

This helps reduce the number of iterations due to invalid constraints.

Design constraints are used to direct synthesis, timing analysis and place and route to meet a chip's timing, area and power requirements.

Poorly designed constraints lead to long implementation design cycle time and the risk of silicon failure and respins.

With design constraints getting larger and more complex, designers are spending significant amounts of time attempting to produce a set of valid constraints.

Until now, there has been no automated solution dedicated to resolve this problem.

Encounter Conformal Constraint Designer addresses the challenges of the new domain of constraint design by generating and validating design constraints, and helping pinpoint the root cause of constraint problems.

'We found Encounter Conformal Constraint Designer to be valuable in helping measure the quality and completeness of constraints across several large blocks of our highest-performance desktop graphics chip', said Karl Pfalzer, Staff Engineer, Desktop Graphics Group, ATI Santa Clara.

'The well-designed interface, consistent with the other Encounter Conformal tools, greatly eased the learning curve'.

'As we embark on our next chip and integrate large portions from several design sites, a quick and easy-to-use measure of constraint quality is a must'.

'We expect Encounter Conformal Constraint Designer to become an integral part of our design flow'.

Encounter Conformal Constraint Designer is the only complete solution available for ensuring valid timing constraints are met throughout the entire design process.

Based on a world-class formal verification engine, it automates the validation and generation of constraints.

Pinpointing real design issues quickly, it also helps accurate achievement of rapid timing closure.

'Encounter Conformal Constraint Designer is the latest innovation in Cadence formal verification technology', said Michael Chang, Vice President of R and D of Cadence Formal Verification Division.

'With this new product, customers finally have an integrated approach to address their constraint challenges'.

Using this technology, designers reduce overall design cycle times and design risk associated with constraints.

Designers also benefit from higher-quality timing constraints for their design implementation, which can significantly enhance quality of silicon (QoS).

It provides a vast improvement over conventional inefficient manual constraint validation and modification methods.

Encounter Conformal Constraint Designer is shipping now.

• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page

Search the Pro-Talk network of sites

Put your news on Electronicstalk  |   Advertise  |   Get the free Electronicstalk newsletter
Electronicstalk Home  |   About Electronicstalk  |   Copyright © 2000-2007 Pro-Talk Ltd, UK