Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 14 December 2004
RTL-to-netlist synthesis speeds
SoCs to market
Toshiba America Electronic Components has introduced a design kit to support its custom SoC and ASIC customers using Cadence Encounter RTL Compiler synthesis
Toshiba America Electronic Components (TAEC) has introduced a design kit to support its custom system-on-chip (SoC) and application-specific integrated circuit (ASIC) customers using Cadence Encounter RTL compiler synthesis. The new kit supports designs for implementing in TC280 (130nm), TC300 (90nm) and newer process technologies.
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Speedy synthesis shrinks ASICs and cuts time
Hitachi Communication Technologies has improved synthesis turnaround time by 50 to 70% with Cadence Encounter RTL Compiler global synthesis
Customers now can use this smooth, qualified flow for RTL-to-netlist synthesis and netlist-to-netlist optimisation with Encounter RTL Compiler.
'We have successfully used SoC Encounter for the past two years to take complex custom designs into production', said Shigenori Imazato, Vice President of Engineering for TAEC Design Centres.
'These have mostly been at TC280 (130nm) technology level'.
Further reading
Comit gains greater access to Cadence technology
Comit Systems has expanded its access to Cadence technology, and has standardised on Encounter RTL Compiler global synthesis, part of the Encounter digital IC design platform
'By adopting Encounter RTL Compiler in addition to SoC Encounter, we have realised a consistent, streamlined flow from RTL-to-GDS'.
'By using the Cadence SoC Encounter RTL-to-GDS flow, we can achieve better performance and faster turnaround time'.
'TAEC has been a long-time user of Encounter RTL Compiler, beginning with its successful use on the world's fastest synthesisable 64bit MIPs core in 2002', said Chi-Ping Hsu, corporate vice president, synthesis solutions, Cadence.
'An increasing number of custom SoC/ASIC vendors such as TAEC are selecting Encounter RTL Compiler as the final synthesis tool in their signoff flow because of its proven ability to increase chip performance, speed turnaround time and produce higher quality of silicon (QoS)'.
QoS measures a design's physical characteristics using wires in terms of improved area utilisation and higher performance.
Optimising QoS is important when designing advanced ASICs and is a significant factor in reducing time to market.
A critical step in the fastest route to superior silicon, Encounter RTL Compiler derives its advantages from its advanced logic structure creation algorithms.
Unlike other synthesis tools that rely on dated, local and incremental optimisation techniques, RTL Compiler applies a global approach that encompasses multi-objective, multilevel and multipath techniques to help achieve higher QoS in less time.
The design kit supporting Encounter RTL Compiler will be available from TAEC by early January 2005.
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