Product category: Design and Development Hardware
News Release from: Cadence Design Systems | Subject: Incisive Palladium II
Edited by the Electronicstalk Editorial Team on 28 October 2004
Emulator tackles complex SoC verification
The new-generation Incisive Palladium II acceleration/emulation system delivers up to twice the speed and capacity of the first-generation Cadence Palladium system
Built on the company's innovative processor-based verification technology, the Palladium II system is targeted at designers verifying the most complex SoCs in the wireless, networking, computing and multimedia markets. The Palladium II system achieves an industry first by reaching 256 million-gate capacity and is just one-third the size of the first-generation system.
This article was originally published on Electronicstalk on 28 October 2004 at 8.00am (UK)
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An integral part of the Cadence Incisive functional verification platform, the Palladium II accelerator/emulator optimises the system design chain by helping companies get to first software and first silicon with even greater speed and efficiency.
Teams can develop and fully verify embedded systems software before receiving first silicon, thereby helping shrink the development cycle dramatically.
In addition, verifying software prior to silicon tapeout enables designers to find bugs that can be fixed optimally in silicon, as opposed to attempting to "patch" the software at a later date.
"As developers of mainframe computers with the largest capacity requirements in the industry, the Palladium II operating in our development lab in Boeblingen, Germany has enabled us to perform concurrent hardware and software co-verification at a high level of productivity", said Kyle VanKleeck, VP Systems Hardware Development, IBM.
"Palladium II has provided the capability to allow a complete virtual power-on which has accelerated the bring-up of our product's development cycle".
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"We have also benefited from the Palladium II's remote multi-user access feature, which has allowed four different development sites around the world to employ the system around the clock, 24 by 7".
The system is the next generation of Cadence's massively parallel Boolean computing engine and processor-based architecture.
Built with advanced sub-100nm silicon, it leverages high-speed on-chip memory, high-bandwidth interconnect, and multi-chip module packaging technology.
This architecture allows direct communication between every processor in the Palladium II accelerator/emulator, enabling fast and efficient communication running at 190MHz.
The new architecture powers the accelerator/emulator engine to achieve the industry's fastest compile time at 10 million to 30 million gates per hour and fastest run-time performance at greater than 1MHz speed.
"At Nvidia, we have deployed over 400 million gates of Palladium II capacity on multiple projects", said Brian Kelleher, Vice President of Hardware Engineering, Nvidia.
"We continue to choose the Palladium family, and in particular the new system, because of the proven performance advantages that the technology has provided for us in the past".
"We are committed to continuing to work with Cadence as the new system provides even faster speed and efficiency, and we anticipate our verification productivity to significantly increase in the coming months.
We look to products like the Palladium II system to help enable us to bring new products to the market on time, critical for success in the multimedia chip arena".
The Palladium II accelerator/emulator allows target connections of up to 61,440 I/Os, enabling verification of a full system or multiple chips running in parallel.
In addition, the multi-user mode can support up to 32 users independently running both in-circuit emulation and simulation acceleration.
The system allows multiple users to access and verify multiple pieces of their hardware and software code, run regression tests or validate different blocks of their design.
The optional remote access feature allows users in multiple locations to collaborate or work separately on various blocks or designs.
The advanced verification environment in the new system provides the most comprehensive support for hardware/software coverification.
Capabilities now include transaction-based acceleration, availability of verification IP, integration with software debuggers, assertion-based acceleration, full support for Linux platforms and broad support of design languages and standards.
The system's high memory capacity enables superior debug capability including InfiniTrace, fast trace upload, dynamic target support, and integration with the Incisive Unified Simulator SimVision debugging environment.
"The technology and performance of our Palladium II system extends Cadence's leadership position in the acceleration/emulation arena", said Christopher Tice, Senior Vice President and General Manager, Verification Acceleration, Cadence.
"Building on our first-generation Palladium solution, we have worked closely with our customers to develop a product that is flexible enough to use today and meet the capacity and speed requirements of tomorrow".
"The Palladium II system provides our customers with what we believe is the best return on investment in emulation/acceleration".
The Incisive Palladium II accelerator/emulator and its advanced verification environment have already been deployed by key customers and are expected to be available to the general public this quarter.
Cadence also offers the new system through Acceleration-on-Demand, its novel licensing model whereby users can swap Incisive Unified Simulator licenses for additional accelerator/emulator capacity at run time.
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