Product category: Design and Development Hardware
News Release from: Cadence Design Systems | Subject: Incisive Palladium verification environment
Edited by the Electronicstalk Editorial Team on 20 July 2004
Emulator offers accelerated SoC verification
Cadence Design Systems has released an advanced verification environment for the industry-leading processor-based Incisive Palladium acceleration/emulation system
The environment, integrated with the Incisive functional verification platform, includes new capabilities that provide the most comprehensive environment for verification of highly complex, multi-million-gate system-on-chip (SoC) designs. Capabilities include enhanced transaction-based acceleration (TBA), verification intellectual property (IP) SpeedBridge solutions, further integration with embedded software debuggers, and additional support for multiple languages and standards - all contributing to greater efficiency for meeting first software and first silicon success.
This article was originally published on Electronicstalk on 20 July 2004 at 8.00am (UK)
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The Incisive TBA solution, based on the standard co-emulation modelling interface (SCE-MI), enhances simulation acceleration performance of the Palladium system by reducing communication between the testbench running on the workstation and the design under test in the emulation system.
Productivity features include support of variable-length messages, a faster streaming mode, transaction recording capabilities and support of both timed and un-timed testbench components.
This solution enables full congruency with the Incisive unified simulator to shorten bring-up time and assure reusability of the testbench and the verification IP models.
"This very comprehensive system-level design and verification methodology encompasses transaction-level abstraction, acceleration and emulation", said Christopher Tice, Senior Vice President and General Manager, Verification Acceleration, Cadence.
"For simulation acceleration users, we provide a complete flow that enables reuse of transaction-level models with high performance".
Further reading
Pattern-synthesis technology acquired
Invarium's pattern synthesis capabilities enable superior pattern resolution and faster yield ramp for designs targeted to 45nm process technologies and below
Logic designers get physical with floorplan data
'Design with physical' approach automatically delivers an accurate physical description of the design into the logic design stage
Timing system is integral part of tapeout success
Atheros Communications has used Cadence Encounter software to design its new AR9001 series of 802.11n chipsets
"For customers delivering the most complex SoC designs in the wireless, multimedia and networking segments, our new vertical solutions improve the efficiency and ease of verification that the Palladium system already delivers".
By combining bus interface solutions, software applications, hardware emulation, real world data connections, and stimulus generated by external testers into one complete environment, chips or entire systems can be comprehensively verified earlier in the development cycle - shaving months from the verification cycle to ensure high-quality, first-pass silicon and reliable software.
The new SpeedBridge solutions available now include PCI Express with support for up to 16 lanes, Multi-Ethernet (10/100Mbit, 1Gbit and 10Gbit) with ability to connect into a "live network" or third-party testers, and video SpeedBridge enhancements.
The USB SpeedBridge solution will be available during H2 2004.
Leveraging Palladium dynamic target capability, a variety of software debuggers can be connected to the emulated design, allowing hardware and software integration and debug flexibility during run time.
"The Cadence PCI Express and RGB SpeedBridges enabled us to emulate our PCI-Express graphics processor design prior to tape-out, developing our software simultaneously to the hardware, and interfacing with the PCI-Express motherboards before our chip was commercially available", said Michael Shiuan, Vice President of Engineering at S3 Graphics.
"The Palladium-based solution is fast and easy to use, and Cadence backed this up with significant PCI Express expertise".
Delivering on the Incisive platform vision of multi-language capability, the environment adds support for Verilog 2001 as a design language and SystemC/System C Verification library (SCV) as a testbench language.
This enables customers to port their code from simulation to Palladium with ease and efficiency, compressing overall verification time.
SystemVerilog will also be introduced in phases starting in H2 2004.
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