Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Design flows for digital nanometre design
Edited by the Electronicstalk Editorial Team on 18 May 2004
Design flows for
digital nanometre design
Design flows for digital nanometre design will be the key theme for Cadence at DAC next month in San Diego, California
TSMC and IBM will demonstrate RTL-to-GDSII 90nm reference flows based on the Cadence Encounter platform. Cadence will complete its Encounter platform for system-on-chip (SoC) devices with the announcement of a global physical synthesis product, delivering the industry's fastest timing and signal integrity closure.
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Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
Methodology combines design with verification
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams
The new tool extends the Encounter tool chain covering from either RTL or a logical netlist to placed gates.
With today's geometries, the percentage of total delay due to wire delay increases significantly.
This makes traditional linear design flows obsolete, because designers cannot afford to go all the way back and change the architecture or logic each time they encounter a problem at the physical implementation level.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Nanometre design also exacerbates physical effects known to introduce significant problems, notably signal integrity (SI) effects and IR (voltage) drop.
Violations can surface late in the design cycle, delaying completion by weeks and requiring tedious manual repairs.
The Encounter platform replaces traditional linear design flows with a completely new design strategy that minimises time to wires and full-chip iteration time.
The platform also ensures the highest QoS.
It provides a nanometre router that optimises wire creation for performance and manufacturability; a unified database with massive capacity of up to 50 million gates; and efficient extensibility.
Highly accurate silicon virtual prototyping technology also makes it fast and easy to model how very complex, high-performance chips will work in silicon.
This prototyping allows you to explore the effects of changes and implement placement, floorplanning, and other critical back-end functions.
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