Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: UMC analogue reference flow kit and MM PDK
Edited by the Electronicstalk Editorial Team on 20 April 2004
Reference flow smooths
out mixed-signal SoC design
UMC and Cadence Design Systems have delivered a jointly developed analogue reference flow that specifically addresses the increasing complexity of mixed-signal designs
The Cadence Virtuoso custom design platform-based reference flow has been silicon-validated using UMC's 0.18-micron mixed-mode CMOS process. Cadence and UMC have developed a process design kit (PDK) that targets the UMC 0.18-micron mixed-mode CMOS process technology. The two companies continue to develop PDKs targeted at the various UMC process technologies and are working to establish an optimised silicon design chain to reduce design risk while enabling the shortest path from design to volume production for mutual customers.
This article was originally published on Electronicstalk on 20 April 2004 at 8.00am (UK)
Related stories
Emulator accelerates IC verification
Winbond Israel found that the Palladium emulator series reduced the overall verification schedule by offering prototype-like runtime performance in a live circuit environment
Mixed-signal verification increases coverage
Simulation enables verification of ultra-low-power sensor interface and transceiver platform for a wide range of healthcare and lifestyle management applications
This best-of-breed 0.18-micron, mixed-mode (MM) PDK is intended to simplify the increasing complexity found in mixed-signal designs.
Ken Liou, Director of UMC's Design Support Division, said: "The analogue reference flow and this newest 0.18-micron MM PDK clearly benefit Cadence and UMC's mutual customers, providing shortened design cycle times and increased assurance that the design will be done right the first time.
We are happy to work with Cadence and its Virtuoso custom design platform to provide silicon-accurate flows that address complex mixed-signal design challenges".
The proliferation of consumer electronics, including wireless technology, has driven the rise in mixed-signal designs.
It is estimated that the total mixed-signal content of an SoC will rise to more than 70% by 2005.
Further reading
Pattern-synthesis technology acquired
Invarium's pattern synthesis capabilities enable superior pattern resolution and faster yield ramp for designs targeted to 45nm process technologies and below
Logic designers get physical with floorplan data
'Design with physical' approach automatically delivers an accurate physical description of the design into the logic design stage
Timing system is integral part of tapeout success
Atheros Communications has used Cadence Encounter software to design its new AR9001 series of 802.11n chipsets
With this increasing complexity, collaboration is critical for producing silicon-validated reference flows and PDKs that will ease the design challenges.
The combination of jointly developed PDKs, proven analogue/mixed-signal solutions from Cadence, and UMC's advanced process technologies enables mixed-signal chip designers to integrate more functionality onto a single chip.
"As the market potential for mixed-signal designs increases, it's critical to develop PDKs and establish proven reference flows to reduce the risk of costly respins that can often result in missing the market window", said Charlie Huang, Corporate Vice President of Business Development at Cadence.
"The combination of UMC's process technology and our leading Virtuoso platform's analogue and mixed-signal design solutions ensures that our customers have a proven path to silicon".
The reference flow uses the Cadence Virtuoso platform and verification technologies to offer a complete and comprehensive solution for analogue and mixed-signal designs.
The Virtuoso platform is the world's first comprehensive platform for fast, silicon-accurate custom, analogue, and mixed-signal design.
Specifically, the UMC analogue reference flow includes the following Cadence technologies: Virtuoso Schematic Editor for schematic capture, Virtuoso XL layout editor, Virtuoso Spectre circuit simulator, Assura design rule checker (DRC) and Assura layout versus schematic verifier (LVS) for physical verification, Assura parasitic extractor (RCX), and Virtuoso analogue design environment for front-to-back analogue design automation for full-custom analogue IC design.
The 0.18-micron MM PDK is one of several PDKs developed by Cadence and UMC as part of a long-term agreement to help integrate UMC process technology with the Cadence front-to-back design and verification flow for analogue and mixed-signal ICs.
The result is a design-through-manufacture path that helps customers meet aggressive product schedules for advanced mixed-signal SoCs.
This PDK provides a symbol library and technology file for the design automation flow and DRC-correct parameterised cells to automate device generation.
They are validated with the Virtuoso Spectre models in the Cadence analogue mixed-signal design solution.
The UMC analogue reference flow kit and 0.18-micron MM PDK are currently available at no charge to Cadence/UMC customers.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
Olympics raises demand for IT contractors
The number of IT contractors working in the engineering sector has almost doubled in 12 months because of demand generated by the 2012 Olympics, according to contractor Giant Group PLC.
Stellar Appoints CIO to Lead Call...
...Centre Outsourcing Technology Strategy. Stellar, a leading global business process outsourcing provider, today announced that Warwick Marx has been appointed Chief Information Officer of Stellar Asia Pacific.
Dell pushes for better Linux drivers
Dell wants to see better software drivers for Linux so that the firm can ship more notebooks and desktops running the operating system, according to one of its software engineers.
Eds Sales Take A Tumble
Dave Friedlos, Computing , Thursday 17 May 2007 at 00:00:00 But experts say downturn may reflect market weakness, writes Dave Friedlos Outsourcing giant EDS has released disappointing first-quarter figures showing slower growth and fewer con



