Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: NanoRoute
Edited by the Electronicstalk Editorial Team on 12 November 2003
Router clocks up a century of tapeouts
A core component of the Cadence Encounter digital IC design platform, the NanoRoute router, has taped out its 100th IC design since its first tapeout just 18 months ago
NanoRoute has been used on leading-edge microprocessor, networking, graphics, telecommunications and other designs in both ASIC/ASSP and COT methodologies. NanoRoute's new-generation graph-based routing architecture delivers unparalleled speed and capacity together with concurrent routing and wire optimisation - key capabilities for nanometre design.
This article was originally published on Electronicstalk on 12 November 2003 at 8.00am (UK)
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NanoRoute simultaneously creates and optimises wires for congestion, timing and signal integrity.
Optimisation is performed on-the-fly during detail routing and is done with complete knowledge of existing net topology, available routing resources, timing and the impact on signal integrity.
NanoRoute also optimises final net routing to minimise critical path delays, reduce wire vulnerability to signal integrity problems and to enhance overall manufacturability.
The result is a design that needs much less "repair" later on in the project.
"We chose NanoRoute as one of the routing engines for NEC Electronics' CB-12 and CB-130, which are the industry's leading ASIC products based on 150 and 130nm, respectively.
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We have had successful tapeout experiences with NanoRoute on several large designs and were impressed by its advantages in SI analysis and prevention.
These advantages helped us on design closure, with the result being a much shorter than expected turnaround time", said Kasu Yamada, General Manager Technology Foundation Development Division, NEC Electronics Corp.
"We expect NanoRoute to show us its full potential as our next-generation routing technology for 90nm and below".
"Our recent tapeout of a 130-nanometre high-speed network processor design, with more than 1.5 million routed nets, marked the first time we used NanoRoute in our production design flow", said Steve Majors, Director of SoC Design Services, Mindspeed Technologies.
"The speed and capacity of NanoRoute was very impressive, but its ability to manage congestion and produce the best-possible timing and noise closure from a given floorplan and placement was significantly better than other routing technologies we have used.
"The most difficult areas of the chip to route could be completed with NanoRoute, where other routers had failed.
In every case, the final routed timing results achieved with NanoRoute were as good as or better than those achieved with other routers.
We plan to make NanoRoute a standard part of our SoC design flow for nanometre design", said Majors.
"It is exciting to see so many leading semiconductor companies adopt NanoRoute for their leading-edge designs.
Achieving 100 tapeouts so quickly is truly a key indicator of technology acceptance and a strong validation of NanoRoute and the Encounter platform in the industry", said Lavi Lev, Executive Vice President and General Manager, Cadence Design Systems.
"Since Plato Design Systems became part of the Cadence family in 2002, the development team has not only remained intact but has nearly tripled in size, while growing its new-generation technology into the best-in-class router that it is today".
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