Product category: Design and Development Hardware
News Release from: Cadence Design Systems | Subject: Palladium
Edited by the Electronicstalk Editorial Team on 18 July 2003
Parallel hardware accelerates verification
Incisive acceleration powered by Palladium has enabled Matsushita Electric Industrial Co to save critical design time and significantly enhance design quality for its complex, nanometre-scale designs
Using the platform's simulation acceleration capabilities, Matsushita increased its verification performance by 1000 times, reducing verification test time from six weeks to 50min. Leveraging this productivity boost, Matsushita was able to run many more tests, resulting in significantly faster time to market for its consumer electronics applications.
This article was originally published on Electronicstalk on 18 July 2003 at 8.00am (UK)
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According to Masanobu Mizuno, Manager at Matsushita's Advanced LSI design Technology Development Co-ordination Group, "Cadence Palladium with its multi-user capability and short turnaround time provided the methodology that enabled us to move easily from simulation to simulation acceleration.
Using the Cadence verification platform to verify our large-scale media processor resulted in a reduction of our overall verification time and improved our design quality.
Palladium compile time is 10 times faster compared to the previous-generation Cobalt accelerator, and run-time performance was improved".
"For the past decade, design teams have consistently reported that functional verification is their biggest design problem - one that routinely consumes more than half of their time, energy and resources", said Christopher Tice, Senior Vice President and General Manager, Verification Acceleration Group at Cadence.
"Matsushita faced this problem in addition to the challenge of verifying massive digital designs with embedded software.
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Phenomenal verification speed and efficiency are required to address these issues.
The Cadence Incisive verification platform, with its unified methodology and single-kernel architecture, is the only platform that enables acceleration-on-demand and a smooth migration from simulation to acceleration and emulation".
Palladium provides acceleration-on-demand within the Cadence Incisive verification platform.
Incisive is the first single-kernel verification platform for nanometre-scale designs that supports a unified verification methodology for the embedded software, control, datapath, and analogue/mixed-signal/RF design domains.
Its unified methodology helps reduce testbench development time, verification runtime and debug time, and can compress overall verification time by up to 50%.
The platform provides native support for Verilog, VHDL, SystemC, the SystemC verification library, property specification language PSL/Sugar, algorithm development and analogue/mixed-signal.
It includes a unique combination of high-performance capabilities: an extensive transaction-level environment; fast, unified test generation; and acceleration-on-demand.
Palladium, used within the Incisive platform or as a stand-alone accelerator/emulator, offers unsurpassed speed and performance with its massively parallel architecture.
Users can share the total capacity of the system, simultaneously and independently accelerating their portions of the design up to and, in some cases, exceeding 100x simulation performance.
Palladium's in-circuit emulation mode supports full system verification by incorporating peripherals, embedded processors, multiple ASICs, embedded software, and real-world data.
Palladium delivers up to 10,000 times faster simulation performance in emulation mode or when regression testing with an embedded testbench.
This level of performance enables the ultimate goal of SoC verification - comprehensive application-level software testing.
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