Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 15 July 2003
Cadence to acquire Verplex Systems
Cadence Design Systems has signed a definitive agreement to acquire Verplex Systems, the acknowledged leader in formal verification electronic design software
The Verplex technology will help Cadence provide customers with formal verification that offers independent verification with best-in-class speed, capacity and debug environment to automate the RTL-GDSII flow. Cadence expects to close the transaction in the third quarter of this year. This acquisition is a key milestone in the company's ongoing platform strategy to provide customers with a complete design-to-volume flow.
This article was originally published on Electronicstalk on 15 July 2003 at 8.00am (UK)
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Cadence will incorporate Verplex's formal verification technology into the Cadence Encounter digital IC platform's nanometre implementation flow, the industry's route to big, fast chips, and Cadence's market-leading Cadence Incisive verification platform.
Cadence also will continue to support Verplex products in alternative flows.
"The next step in our overall strategy, Verplex is an integral part of the fabric of technologies required by power users and the most aggressive designers, and it has, in a very short time, become the standard for designing high-performance chips", said Ray Bingham, President and CEO of Cadence.
"This technology has rapidly won over customers to capture the top half of the market - leaders in the semiconductor industry - and now gives us a significant edge in helping customers solve their most difficult problems.
Verplex expands Cadence's leadership, has no overlapping technology with existing Cadence technology, enabling independent verification, and brings in a world-class technology team and leaders".
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A recent independent study indicated that more than half of all chips required one or more respins, and that functional errors were found in 74% of these respins.
Verplex's solution addresses this challenge by detecting functional differences between successive revisions of a chip design from RTL to GDSII, and includes unique datapath, digital custom and memory verification capabilities.
"The addition of Verplex's leading technology complements the Cadence Encounter and Incisive platforms' superior prototyping, routing, signal integrity, synthesis and single-kernel verification capabilities", said Ping Chao, Senior Vice President and General Manager at Cadence.
"Independent formal verification is an integral component of a high-end nanometre chip design flow.
It will enable customers to handle verification of even bigger, faster chips".
"The Verplex team is excited to be part of Cadence during this period of challenge and growth", said Michael Chang, President and CEO of Verplex.
"Verplex's products are rated number one in speed, capacity and usability.
Our companies' technologies are highly complementary and will extend Cadence's ability to provide technology to design big, fast chips by adding independent formal verification to its nanometre IC implementation and verification flows".
Design closure is achieved when an implemented design meets its performance specifications.
A logically correct register transfer level (RTL) design, or golden RTL, still undergoes massive transformations and iterations before final layout.
Each step in this process can introduce logical inconsistencies, or bugs.
As IC designs grow in size and complexity, the importance of independent formal verification grows.
"Agilent Technologies has successfully leveraged leading-edge technology from both Cadence and Verplex to meet our aggressive product cycles and customers' turn-around requirements", said Richard Nash, Director of Engineering for Agilent's ASIC Products Division.
"We believe that the combination of these solutions will provide even better results and will further improve our ability to ensure schedule predictability and time-to-market in our nanometre design flow".
"We find that formal verification is mandatory technology for a successful automated design flow", said Shardul Kazi, Vice President of the TX RISC Business Unit at Toshiba America Electronic Components.
"Cadence tools meet our nanometre design needs for creating multi-million-gate application specific standard products and custom system-on-chip designs.
By bringing the Verplex technology into the Cadence solution, we look forward to even higher-quality results and improved time-to-market".
A roadmap for the incorporation of Verplex's products is currently under development.
This will include Conformal LEC logic equivalence checker, Conformal LTX logic transistor extractor, Conformal FPGA equivalence checker, Conformal LVR layout versus RTL, Conformal MEM memory equivalence checker, Conformal Datapath circuitry checker and BlackTie assertion-based verification.
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