Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence RTL Compiler
Edited by the Electronicstalk Editorial Team on 19 May 2003
Compiler speeds chipset to market
The Cadence RTL Compiler has helped Teradiant Networks to accelerate the development of its TeraPacket chipset, which comprises a network processing engine and traffic manager
The more than 200-million-transistor chipset has been deemed to be among the densest semiconductors designed to date. It took Teradiant eight months to design TeraPacket using Cadence RTL Compiler, a high-speed, high-capacity tool for register transfer level (RTL) synthesis of multi-million-gate integrated circuits targeting advanced foundry process technology.
This article was originally published on Electronicstalk on 19 May 2003 at 8.00am (UK)
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Cadence RTL Compiler's breakthrough global-focus algorithms enabled improved speed and die area, with significant enhancements in runtime and memory consumption over other market solutions.
"Teradiant's work with RTL compiler enabled the design of TeraPacket", said Satchit Jain, Chief Executive Officer of Teradiant Networks.
"RTL Compiler helped us meet the demand by networking equipment OEMs for high-ROI enabling semiconductors that will drive the growth of next-generation Internet routers, multi-service switches and metropolitan switches.
Teradiant's aggressive design goals led us to select Cadence as our design automation partner".
"Having defined a chip architecture that delivers flexibility, high performance, and significantly reduced time-to-market, Teradiant Networks has demonstrated its leadership in the network processor segment", said Ping Chao, Senior Vice President and General Manager of the Encounter platform at Cadence.
"We are delighted that Teradiant worked with us to build this remarkable chipset".
Cadence purchased RTL Compiler with its recent acquisition of Get2Chip.
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