Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Advanced Package Designer V15.0
Edited by the Electronicstalk Editorial Team on 13 March 2003
Package design suite
simplifies die stacking
Cadence Design Systems has developed a new capability for designing stacked-die packages
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Such devices are growing in popularity as a result of manufacturers' need to increase functionality in an ever-shrinking design envelope. Stacked-die packages are particularly common in cellphones, digital cameras and hand-held devices, which require the faster turnaround, higher levels of integration and lower costs found in system-in-package (SiP) solutions.
"Stacked-die packaging is pervasive in the wireless and memory markets because it facilitates both portability and performance", said Bret Zahn, Vice President of Worldwide Design and Characterisation, ChipPAC.
"ChipPAC, as the market leader in stacked-die package design, assembly and test, sees the new Cadence capability as a way to be more productive and to provide the highest-performance, most cost-effective design solutions to our customers".
"Using stacked-die packaging allows designers to free up valuable real estate on both the package and the board", said Charlie Giorgetti, Corporate Vice President and General Manager of the Cadence PCB Systems Division.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
"But, designing an interconnect plan for a stack of chips is a complicated process.
Our new technology is designed to simplify this process, and help manufacturers get products designed and in volume production quickly".
Today, virtually all stacked-die packages use wire bonding for the interconnect to the substrate; a single package design may have hundreds of wires and multiple-bond patterns for various die combinations on a single substrate.
To address this complexity, the new wire-bonding capability automates the design process and addresses reliability issues through advanced wire spacing and automated realignment features.
Integrated into the Cadence Advanced Package Designer suite, this capability supports all phases of design, from concept to manufacturing file output.
Important features include the ability to bond as many die as desired; use different spacing rules for each die and quadrant; and create multiple bonding patterns so that one substrate can handle multiple-die combinations.
Cadence Advanced Package Designer also provides the capability to combine flip-chip and wire-bond die in the same design.
The stacked-die automated wire-bonding capability is part of Cadence Advanced Package Designer version 15.0, expected to be available in the second quarter of 2003.
The product is supported on Solaris, HP-UX, IBM-AIX platforms, XP Pro, Windows NT and 2000.
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