Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 14 January 2003
Tool suite passes signal integrity test
TSMC and Cadence Design Systems reckon they have successfully resolved key signal integrity (SI) issues in 130 and 90nm process technologies
As a result, TSMC has qualified the Cadence tool suite to be included in the next generation TSMC Reference Flow. "TSMC's expertise in developing design methodology for advanced silicon technologies coupled with Cadence's design automation strength is a powerful combination", said Genda Hu, Vice President of Corporate Marketing at TSMC.
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"We are pleased that our collaboration with Cadence to develop TSMC Reference Flow 4.0 has made significant progress.
The integration, performance, and capacity of Cadence SoC Encounter system have been proven with real nanometer circuit design examples.
We anticipate this Reference Flow 4.0 will enable our customers to greatly shorten the design cycle and to maximise first-pass silicon successes when using TSMC's advanced technologies".
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"A close relationship between our foundry and our design technology partner is an important factor for our success at 130nm and below", said Greg Buchner, Vice President of Engineering at ATI Technologies.
"We are very pleased to see TSMC and Cadence collaborate closely on key issues such as signal integrity closure".
TSMC's Reference Flow 4.0 will incorporate the Cadence Encounter system from virtual prototyping to physical implementation.
This complete system enables designers to account for signal-integrity effects early in the design process, and to make systematic, predictable progress toward signal-integrity signoff.
"TSMC continues to develop and provide its customers with advanced design methodologies to better utilise its industry leading process technologies", said Charlie Huang, Corporate Vice President of Business Development at Cadence.
"We are very happy to further strengthen and enhance our partnership with TSMC, and collaboratively solve difficult nanometer design challenges such as full-chip signal integrity and timing closure.
We look forward to continued collaboration in the future".
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