Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: CeltIC 4.0
Edited by the Electronicstalk Editorial Team on 13 August 2002
Signal-integrity tools tackle nanometre crosstalk
The latest release of the CeltIC signal integrity solution includes major enhancements critical to successful nanometre design
The latest release of the CeltIC signal integrity solution, the recommended crosstalk analysis tool in the TSMC 130nm reference design flow, includes major enhancements critical to successful nanometre design. CeltIC 4.0 features greater capacity of more than five million gates flat, to handle the increased scale of nanometre designs.
This article was originally published on Electronicstalk on 13 August 2002 at 8.00am (UK)
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Signal integrity problems are a first-order effect in nanometre designs, where tall, thin wires create unintended electrical effects that impact design timing and functionality.
CeltIC 4.0 signal integrity analysis enables customers to identify these signal integrity problems before their designs are committed to silicon and to avoid costly and time-consuming re-spins.
Tightened integration of CeltIC 4.0 with Cadence SoC Encounter and Cadence Silicon Ensemble PKS (SE-PKS) provides integrated crosstalk minimisation, analysis, and repair throughout customers' IC design flows.
CeltIC 4.0 includes support for 32bit Linux and IBM AIX operating systems, and for 64bit workstations from Sun Microsystems and Hewlett Packard.
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Cadence customers AMD, Agere Systems and Metalink have achieved accelerated signal integrity closure and faster time-to-market with CeltIC.
According to John J Szetela, manager, CAD engineering and systems for AMD's Personal Connectivity Solutions Group, "AMD has used CeltIC for crosstalk signoff on four tapeouts, including our most recent 130nm networking design.
We are impressed with CeltIC's filtering of false errors, which lets us focus on the few real noise failures, thereby achieving quicker signal integrity closure on our IC designs.
We beta-tested CeltIC 4.0's Linux port, and it demonstrated a 3X speedup over previous versions.
This acceleration should help us get our multi-million-gate designs to market faster".
"Agere Systems validates its IC and ASIC designs before tapeout to ensure they are noise immune", said Kishore Singhal, manager for signal integrity and interconnect analysis with Agere Systems.
"The company has successfully used CeltIC to check and repair crosstalk violations for a number of designs, including our larger, more highly integrated ASIC system solutions.
Agere's ASIC business has benefited in particular from the improved accuracy of CeltIC 4.0 in analysing electrical noise and other problems.
Maintaining signal integrity enables us to meet two of our ASIC customers' primary needs: increased high-speed interface channels and reduced time-to-market".
"To eliminate costly mask changes and silicon re-spins, it is imperative that our leading-edge DSL chip sets be free from noise problems", said Yuval Itkin, director of the VLSI group with Metalink.
"Using CeltIC allowed us to successfully detect an elusive crosstalk-induced problem in time on our 0.18-micron design.
We have incorporated CeltIC into our design flow for crosstalk signoff of all future designs".
CeltIC 4.0 creates crosstalk repair files that drive the in-place-optimisation (IPO) engines of SoC Encounter and SE-PKS to implement the fixes.
Fixes include resizing victim drivers, inserting buffers, spacing aggressors away from victims, and shielding failing nets.
CeltIC 4.0 provides greatly increased capacity and has been used on nanometre-scale designs of more than five million gates flat on standard 32bit workstations.
In addition, CeltIC 4.0 delivers improved accuracy, including modelling the nonlinear slew degradation on victim nets that affects the rise-and-fall delays of the receiver cells.
Also new is support for the more accurate BSIM4 and MOS9 device models.
"With this new release of the CeltIC signal integrity solution, Cadence customers will benefit from improved chip yields and performance by addressing signal integrity at all stages of the design flow including virtual prototyping, block implementation, and final signoff", said Eric Filseth, vice president of SP and R marketing at Cadence.
"The integrated Cadence solution enables our customers to rapidly achieve signal integrity closure as they progress from RTL to GDSII".
(This was Electronicstalk's Top Story on 13 August 2002)
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