Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 26 April 2002
Cadence completes Plato acquisition
Cadence Design Systems has completed its acquisition of Plato Design Systems.
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Cadence Design Systems has completed its acquisition of Plato Design Systems. The financial terms of the agreement were not disclosed. NanoRoute, Plato's next-generation graph-based router, will improve the Cadence SP and R (synthesis/place-and-route) technology with performance, timing and signal integrity enhancements targeted at 0.13-micron-and-below design.
Initially, NanoRoute will be incorporated as an option into Cadence SoC Encounter, Cadence's hierarchical IC implementation technology.
"The acquisition of Plato is another major step in our strategy to integrate world-class technologies into Cadence's best-in-class solutions for chip designs at deep sub-micron process geometries", said Lavi Lev, executive vice president and general manager for Cadence IC business unit.
"Additionally, Plato's world-class development team brings additional capability to Cadence's existing routing research and development group".
"This merger allows us to quickly deliver our technologies to many more customers and extends our ability to respond to customers' needs", said Limin He, president and CEO of Plato.
"This also affords us a great opportunity to integrate our complementary technologies tightly with Cadence 's technologies and help customers address the design challenges of deep sub-micron SoCs".
All 26 Plato employees will join Cadence.
Limin He will report to Ping Chao, Cadence senior vice president and general manager of Digital IC Solutions.
NanoRoute is a scalable routing and physical design optimisation solution.
By cutting routing time from days to hours, NanoRoute plays a key role in closing the gap between design productivity and advances in silicon technology.
It will significantly enhance the current capabilities of Cadence SoC Encounter and First Encounter Ultra by enabling designers to better meet deep submicron challenges in 0.13-micron-and-below designs.
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