Click on the advert above to visit the company web site

Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Advanced Hardware Architectures
Edited by the Electronicstalk Editorial Team on 19 November 2001

Design flow speeds multi-million-gate design

Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow

Advanced Hardware Architectures' (AHA) Fiber Division has designed and taped-out a 10-million-gate forward error correction (FEC) IC using the 64bit Cadence SP and R (synthesis/place-and-route) design flow. To design the 200MHz FEC, dubbed Project Neptune, on UMC's 0.18-micron process technology, AHA used Silicon Ensemble-PKS (SE-PKS) optimisation place-and-route solution from RTL to GDSII, including full-chip, post-route timing analysis in less than one hour.

"We have demonstrated that Cadence 64bit SP and R technology can handle very large designs and mitigate the risk of missing goals", said Tim Heldt, staff EDA engineer, whose 10-million-gate 200MHz chip was the largest designed and taped-out by AHA.

Jeff Hannon, Neptune's project manager, further reinforced this position by saying, "Cadence SP and R is a powerful flow.

Hundreds of designers would typically work 18 months on a chip of this magnitude, yet we met our timing and area goals in 12 months with a staff of about 20 designers, many of whom were not on the project full time".

AHA specialises in the design of chips that embody its proprietary error-detection and correction algorithms for communications applications.

The Project Neptune design represents the third chip that AHA's Fiber Division has successfully designed and taped-out this year using Cadence SP and R design technology.

The two prior SP and R designs - a 400-thousand-gate and a 2.5-million-gate design - resulted in successful first silicon.

Because of Project Neptune's need for large capacity, AHA used a hierarchical physical design methodology in the SP and R flow leveraging the full complement of powerful and comprehensive technology engines in SE-PKS.

AHA's SE-PKS design flow included: initial floorplanning; synthesis of all blocks for timing convergent, global-routed block placement; testability using pivotal scan insertion and placement-based scan chain reordering; datapath-intensive block area reduction and performance optimisation; optimisation at the top-level with abstracted blocks and global-routed timing convergence with world-class routing engine in SE-PKS; final detail routing of all levels in the design hierarchy; and full-chip static timing analysis and final timing signoff with integrated timing engine.

"We are delighted with AHA's repeated tape-out success using the Cadence SP and R flow", said John Murphy, vice president, Cadence SP and R.

"The sheer size and complexity of Project Neptune and its success is a testament to the capability of AHA's design team, and is another example of the superior capacity, performance, and quality of results achieved with SP and R".

• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page

Search the Pro-Talk network of sites

Put your news on Electronicstalk  |   Advertise  |   Get the free Electronicstalk newsletter
Electronicstalk Home  |   About Electronicstalk  |   Copyright © 2000-2007 Pro-Talk Ltd, UK