Product category: Design and Development Software
News Release from: ARC International | Subject: ARChitect
Edited by the Electronicstalk Editorial Team on 28 June 2006

Processor configuration tool Encounters support

Using ARChitect, ARC licensees now can produce RTL, synthesis and floorplanning scripts that are tuned to the Encounter reference methodology

In sub-100nm process geometries, capacitance, inductance, resistance and crosstalk all conspire to thwart a design team's efforts to produce right-first-time silicon that meets critical timing and power budgets. To address this industry-wide challenge, Cadence Design Systems and ARC International have integrated optimised support of the Cadence Encounter digital integrated circuit (IC) design platform into ARC's patented ARChitect processor configuration tool.

Using ARChitect, ARC licensees now can produce RTL, synthesis and floorplanning scripts that are tuned to the Encounter reference methodology.

This will help the system-on-chip (SoC) designer better anticipate the behaviour of electrical signals and ensure the design is fully verified before going to silicon.

The companies also announced that ARC has joined Cadence's OpenChoice IP Programme and become one of Cadence's featured intellectual property (IP) partners.

'By collaborating with ARC International, our mutual customers can get to market quickly with highly optimised silicon through the use of best-in-class configurable and EDA technologies', said Jan Willis, Senior Vice President of Industry Alliances at Cadence.

'Through the OpenChoice IP program, Cadence and ARC will continue to work together to ensure SoC designers using our products continue to benefit from the fruits of our deepening partnership'.

The Cadence Encounter Digital IC Platform provides an integrated RTL-to-GDSII design environment - from RTL synthesis and test design through physical prototyping and partitioning to final timing and manufacturing closure.

Encounter offers highest quality of silicon (timing, area, and power with wires), accurate verification, SI-aware routing, and the latest yield and low power design capabilities that are critical for the advanced designs of ARC's customers.

'Cadence Encounter design platform provides a proven path to silicon for all of the ARC 600 and ARC 700 configurable core families and multimedia subsystems by characterising and accommodating all the circuit effects that proliferate in the interconnect layers of nanometre processes', said Peter Hutton, Senior Vice President of Engineering at ARC.

'Thus our customers can let the tool handle the noncreative part of the design flow, freeing them to be creative using the ARChitect processor configuration tool to add or remove components in ARC cores to achieve additional functionality - enabling higher margins and more differentiation from competitors'.

'We look forward to continuing our close collaboration with Cadence through the OpenChoice IP programme'.

ARChitect Processor Configurator enables SoC designers to rapidly create customised ARC processor core designs optimised for specific applications, without increasing project complexity or risk.

Using the ARChitect tool's drag-and-drop GUI, designers can include features they need and remove those not needed for their application.

Configuration options include features around the core such as type and size of caches, interrupts, DSP subsystems, timers and debug components, as well as features within the core such as type and size of core registers, address bus widths, and instruction set options.

Performance and die size tradeoffs are quickly accomplished, resulting in an optimised solution.

The resulting core invariably will be smaller and lower power than 'fixed architecture' cores.

The Cadence Encounter reference methodology integrated into ARChitect allows designers to quickly create a detailed, full-chip, silicon virtual prototype including characterised routed wires.

Integral to the platform is a flexible graphical user interface, a customised flow, the ARC 600 or ARC 700 configurable core families reference designs, and a base technology/library infrastructure.

The methodology provides completely validated synthesis and floorplanning scripts to enable users to implement the latest technology quickly, with minimal ramp-up time.

The Cadence OpenChoice IP programme enables interoperability and facilitates open collaboration with leading IP providers to build, validate, and deliver accurate models for Cadence design and verification solutions.

The program aims to ensure IP quality, integration, and provides engineers access to a broad IP offering through a complete IP catalogue.

This optimises the electronics design chain and accelerates customer time to market.

The ARChitect processor configuration tool with integrated optimised support of the Cadence Encounter digital integrated circuit (IC) design platform is available immediately.

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