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Product category: Design and Development Software
News Release from: Ansoft Europe
Edited by the Electronicstalk Editorial Team on 13 September 2005

Paper outlines serial
interconnect design flow

A new white paper unveils the technical details of a reference design flow for high-speed serial interconnect

At last months Intel Developer Forum Ansoft presented a white paper unveiling the technical details of a new reference design flow for high-speed serial interconnect. The design flow addresses the needs of high-speed design engineers to simulate and optimise multigigabit serial buses, such as PCI Express.

Leveraging the fast, high-capacity circuit simulation of Nexxim with the integrated 3D parametric electromagnetic model extraction of HFSS, this new reference flow enables designers to fully explore design possibilities to achieve greater performance and reliability.

The white paper was distributed at the Intel Developer Forum and was provided to delegates on the conference CD.

It is now available as a free download from the Ansoft website.

Engineers designing servers, storage devices, multimedia PCs, entertainment systems and telecom systems have driven an industry trend to replace legacy-shared parallel buses with high-speed, point-to-point serial buses.

Standard interfaces, such as XAUI, XFI, Serial ATA, PCI Express, HDMI and FB-DIMM have emerged to provide greater throughput using serial signalling rates of 2.5 to 10Gbit/s.

Although this trend has greatly reduced the number of traces and connections within the system, it has created new challenges for electronic system designers when considering implementation with multiple connectors, transmission lines, vias, IC packaging and transceiver circuits.

'Fast edge rates in modern serial links produce gigahertz-frequency harmonics that can only be modelled with full-wave electromagnetics', said Dr Lawrence Williams, Ansoft's Director of Business Development.

'Ours is the only solution that accurately predicts link performance with nonlinear drivers and receivers, S-parameters and W-elements while fully managing the design'.

Performing simulations on high-speed serial interconnects presents two primary challenges: simulation limitations and design management.

Complex interconnects contain passive and active components, including line drivers/pre-emphasis circuits, IC packaging, lossy microstrip and stripline transmission lines, layer-to-layer via structures, connectors and line receiver/equaliser circuits.

Characterising these elements requires detailed simulation in the frequency and time domains.

Frequency-domain analysis is used to examine channel spectral response for insertion loss and return loss.

Time-domain analysis is used to simulate transient behaviour, such as eye diagrams, jitter and time-domain reflectometer (TDR) response.

Managing the design with models from multiple vendors, measurements or electromagnetic simulation requires the ability to assemble the models into a single simulation.

Once assembled, technology for simulation must be able to handle gigahertz frequencies, time- and frequency-domain simulations and highly complex designs that require high capacity.

Ansoft has solved both challenges with a combination of advanced circuit and electromagnetic simulation technology and an integrated design environment for design management.

The reference design flow uses Solver on Demand automation features in DesignerSI to support alteration of component model representation prior to simulation.

Solver on Demand automatically links the electromagnetic-field simulator with the circuit simulator to intelligently add electromagnetic accuracy to the overall channel simulation.

The electromagnetic simulations can be varied, producing a simulation that not only accounts for variation in supplied circuitry, but variations in geometric designs by the end user.

The design flow provides a method to accurately and efficiently simulate the individual components of the physical layer, including the package, connectors, motherboard and addon cards.

The package, connector and motherboard can be combined so that the entire channel can be simulated and verified early in the design phase, saving time and costly design respins.

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