Product category: Analogue and Mixed Signal ICs
News Release from: Analog Devices | Subject: AD9245
Edited by the Electronicstalk Editorial Team on 25 February 2003
Frugal ADC shrinks
to chip-scale package
Analog Devices has developed the industry's first 3V, 14bit, 80Msample/s A/D convertor with breakthrough sub-500mW power consumption
This low-power ADC augments ADI's family of high-speed ADCs available in chip-scale packages (CSP), including pin-compatible 10 and 12bit versions that were announced in September 2002. ADI's CSPs deliver the same levels of performance in packages that are 87% smaller than previously offered packages.
This article was originally published on Electronicstalk on 25 February 2003 at 8.00am (UK)
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"Wireless infrastructure manufacturers and carriers are looking to ease design challenges and cut cost as they drive the adoption of next generation wireless standards", said Kevin Kattmann, Product Line Director for High-Speed Convertors, Analog Devices.
"The low power and small size of our ADCs in chip-scale packaging allow wireless engineers to design more cost effective radios while maintaining current levels of performance".
The new chip, the AD9245, is suitable for picocell and microcell designs with multiple base stations on one tower, or locations where low power consumption is advantageous, such as distributed base stations for "hot spots" or in buildings where medium network capacity is needed.
It also enables migration from single-carrier to multicarrier platforms, allowing designers to keep costs down while maintaining 14bit performance.
The AD9245 uses a multistage differential pipelined architecture with output error correction logic to provide 14bit accuracy at 80Msample/s datarates, and guarantees no missing codes over the full operating temperature range.
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It operates with a signal-to-noise ratio (SNR) of 72dB and spurious-free dynamic range (SFDR) of 85dBc.
It is pin compatible with the AD9235 12bit, 20/40/65Msample/s ADC, AD9236 12bit, 80Msample/s ADC, and AD9215 10bit, 65/80/105Msample/s ADC.
The sample-and-hold amplifier (SHA) features a proprietary input sampling network that can be configured for single-ended or differential operation, thus eliminating the expense of a single-ended to differential conversion stage in a single-ended system.
A clock duty-cycle stabiliser allows the AD9245 to maintain performance over a wide range of clock pulse widths.
This is important to portable applications in which the clock source may be less than ideal.
Fully compatible with ADI's entire family of 32-pin LF-CSP packaged ADCs, the AD9245 gives designers a simple upward migration path, allowing a single analogue front-end signal chain to be used in various products, with performance that can be differentiated based on the chosen ADC.
The AD9245 supports input frequencies as high as 100MHz, helping to eliminate a down-conversion stage and reduce the number of components needed to complete the design.
In addition, components such as mixers and filters become unnecessary, ultimately lowering total system cost.
Power-sensitive multichannel applications such as ultrasound and high-end medical imaging also benefit from the AD9245's sub-500mW power consumption.
The AD9245 is packaged in a 32-pin CSP and is priced at $38.00 per unit in 1000-piece quantities.
Samples and evaluation boards are available now.
Full production is scheduled for April 2003.
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