Product category: Microprocessors, Microcontrollers and DSPs
News Release from: AMI Semiconductor | Subject: XPressArray 1.5V
Edited by the Electronicstalk Editorial Team on 25 November 2002
ASIC technology aims
for budget FPGA replacement
AMI Semiconductor has outlined the next phase in the roadmap for its high-performance, low-power hybrid gate array solutions with the launch of a 1.5V version of its popular XPressArray technology
AMI Semiconductor (AMIS) has outlined the next phase in the roadmap for its high-performance, low-power hybrid gate array solutions with the launch of a 1.5V version of its popular XPressArray technology. Aimed at medium-density, low power 1.5V ASICs and FPGA-to-ASIC conversions, the new 1.5V XPressArray platform is ideal for developing cost-effective ASIC replacements for FPGAs such as Virtex II from Xilinx and Stratix from Altera.
This article was originally published on Electronicstalk on 25 November 2002 at 8.00am (UK)
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These replacements can be pin-for-pin compatible with the FPGA parts, or developers can choose to reduce size and component count by converting multiple FPGAs to a single XPressArray ASIC.
The original 1.8V XPressArray technology was launched in January 2002 and is being deployed in a variety of communications and network storage applications.
Based on the same hybrid technology, the 1.5V XPressArray offers lower power designs the same benefits of reduced unit price, 14-day prototyping from design signoff, and NRE (nonrecurring engineering) cost savings of up to 70%.
ASICs based on the 1.5V XPressArray gate array platform offer densities of up to 2.6 million gates and system clock speeds of up to 150MHz, which is comparable to the logic performance of leading 1.5V FPGAs.
A power dissipation of 0.035uW/MHz per gate represents a 30% improvement over the original 1.8V XPressArray technology.
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In addition to communications and storage, applications for 1.5V XPressArray also include designs in the industrial, automotive, consumer and medical arenas.
XPressArray devices are fabricated using a hybrid process that integrates a leading edge front-end process from Taiwan semiconductor manufacturing Co (TSMC) with a proven AMIS metal finishing technology.
Similar to FPGAs, the TSMC processing expenses for prefabricated base array slices are shared across many applications.
For each customised application, the AMIS metal tooling and manufacturing costs are significantly lower than for cell-based processes, resulting in the low NREs, low unit costs and fast cycle times associated with gate array metal finishing.
Discussing the launch of 1.5V XPressArray, Vince Hopkin, Vice President of Digital ASICs at AMIS, comments: "As we projected at its launch, the original 1.8V XPressArray platform allows customers to realise the performance and low-power operation of advanced processes without the cost or cycle time penalties associated with 'bleeding edge' technology.
We are now building on the success of this technology by launching the 1.5V version of the platform in line with the timescales indicated by our original roadmap".
XPressArray hybrid gate arrays can be configured with up to 200k internal registers and between 38Kbit and 1.4Mbit of embedded configurable and initialisable memory.
Flexible I/O configurations include support for a wide variety of common standards including LVTTL, LVCMOS, PCI, HSTL, SSTL, GTL/+, LVPECL, LVDS and BLVDS.
The technology is compatible with 1.5, 1.8, 2.5, 3.3 and 5.0V I/O schemes, while comprehensive clock management circuitry includes options for up to 12 all digital delay-locked loops (DLLs) and a maximum of four phase-locked loops (PLLs).
Embedded scan test logic is included to facilitate high fault coverage testing.
Rapid access to the XPressArray hybrid gate array technology can be achieved using the AMIS Netrans FPGA-to-ASIC conversion methodology.
In addition, XPressArray synthesis libraries are available for leading commercial synthesisers such as Synplicity's Synplify ASIC and Synopsis Design Compiler.
Using the AMIS RTL hand-off flow tool, designers can submit RTL descriptions, scripts and timing constraints and AMIS will check, synthesise, layout and achieve timing closure of the design.
(This was Electronicstalk's Top Story on 23 November 2002)
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